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3-channel 8-bit 165msps a/d converter amplifier pll description the CXA3516R is a 3-channel 8-bit 165msps a/d converter with built-in amplifier and pll developed for lcd projectors and lcd monitors. the CXA3516R inputs rgb graphics signals from personal computers or others. after the input levels are controlled, the a/d conversion is performed with a clock generated by pll. the digital output levels are compatible with ttl. this ic operates at a maximum conversion rate of 165mhz, and can support up to uxga. control register supports both i 2 c and 3-wire bus. features supply voltage: 5v, 3.3v power consumption: 1.8w typ. (165msps) 144-pin lqfp 3-ch amp and pll eliminate design time for mutual connections. structure bipolar silicon monolithic ic applications lcd monitors lcd projectors digital tvs pdps functions and performance power save function supports both i 2 c and 3-wire bus amplifier block clamp main contrast: 8-bit sub contrast: 8-bit 3 main brightness: 8-bit 3 cbcr offset: 6-bit 2 supports ycbcr input two input systems amp monitor output/sw monitor output syncsep function a/d converter block maximum conversion rate: 165msps supports uxga input supports demultiplexed output supports both in-phase and alternate phase during demultiplexing supports yuv4:2:2 output output high impedance mode built-in reference voltage pll block sync input frequency: 10khz to 130khz clock delay: 1/32 to 64/32clk vco counter: 12-bit low clock jitter clk inversion clk and 1/2clk outputs ?phase comparison hold ?output high impedance mode ?1 e99y28a07-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA3516R 144 pin lqfp (plastic)
?2 CXA3516R absolute maximum ratings (ta = 25?) item dv cc reg, av cc adref, dv cc adttl, dv cc ad, dv cc pllttl, av cc vco, dv cc pll, av cc ir, av cc ampr, av cc ampg, av cc ampb av cc ad3, dv cc ad3 address, xpowersave, xsenable, 3wire/i 2 c, hold, xtload, even/odd, xclkin, clkin, syncin1, syncin2, clpin, rc1, rc2, r/crin1, r/crin2, r/crclp, g/yclp, b/cbclp, sogin1, g/yin1, sogin2, g/yin2, b/cbin1, b/cbin2, rcrout, g/yout, b/cbout, dactestout sda, scl tstg p d supply voltage input voltage storage temperature allowable power dissipation 5.5 5.5 gnd ?0.5 to 5v v cc + 0.5 or 5.5 gnd ?0.5 to 5.5 ?5 to +150 5 v v v v ? w maximum ratings unit recommended operating conditions item dv cc reg, av cc adref, dv cc adttl, dv cc ad, dv cc pllttl, dv cc pll, av cc vco, av cc ir, av cc ampr, av cc ampg, av cc ampb av cc ad3, dv cc ad3 xpowersave, hold, xtload, even/odd, syncin1, syncin2, clpin clkin, xclkin straight mode dmux mode yuv4:2:2 d2 mode yuv4:2:2 special mode ta supply voltage ttl input pin pecl input pin maximum conversion rate operating ambient temperature 4.75 3 2 dv cc pll ?.8 100 165 100 100 ?0 5 3.3 5.25 3.6 0.8 dv cc pll ?.6 +75 v v v v v v msps msps msps msps ? max. typ. min. unit high level low level high level low level
?3 CXA3516R pin configuration (top view) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 1 2 3 4 121 122 123 124 125 126 127 128 129 130 131 132 142 143 144 110 109 111 112 113 114 115 116 117 118 119 120 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 36 11 21 31 b/cbout address r/crout nc nc xpower save dgndreg dv cc reg sda scl xsenable serout 3wire/i 2 c dpgnd av cc adref av cc ad3 vrt dv cc ad3 dv cc adttl dgndadttl ra0 ra1 dgndad3 ra2 ra3 ra4 ra5 ra6 agndad3 dgndad3 ra7 dv cc adttl dgndadttl rb0 rb1 rb2 ga4 ga3 ga2 ga1 ga0 dgndadttl dgndad3 dv cc adttl bb7 bb6 bb5 bb4 bb3 gndad3 bb2 bb1 bb0 dgndadttl dv cc adttl ba7 ba6 ba5 dgndad3 ba4 ba3 ba2 ba1 ba0 dgndadttl dgndad3 dv cc adttl rb7 rb6 rb5 rb4 rb3 even/odd xtload hold sogout unlock dsync/divout dpgnd 1/2clk 1/2xclk clk xclk dgndpllttl dv cc pllttl agndadref av cc ad3 vrb dv cc ad3 dv cc ad dv cc adttl dgndadttl gb7 gb6 dgndad3 gb5 gb4 gb3 gb2 gb1 agndad3 dgndad3 gb0 dgndadttl dv cc adttl ga7 ga6 ga5 xclkin clkin syncin1 syncin2 clpin dv cc pll dgndpll av cc vco agndvco rc1 rc2 av cc ir iref dpgnd agndir g/yin1 av cc ampg g/yin2 agndampg g/yclp b/cbclp r/crclp dpgnd sogin1 b/cbin1 av cc ampb sogin2 b/cbin2 agndampb dpgnd r/crin1 av cc ampr r/crin2 agndampr g/yout dactestout
4 CXA3516R amp r sw r amp g amp b adc r adc g adc b sw sw g sw b syncsep syncsep syncsep sw pll pd pll cp (3) fine delay (6) width (2) coarse delay (2) vco div 1, 2, 4, 8 register address sogout xpower save sda scl xsenable serout 3wire/i 2 c hold xtload rc1 rc2 counter (12) 1/2div unlock sub contrast (8) sub brightness (8) r/crin1 clpin r/crout r/crin2 r/crclp g/yclp g/yin1 g/yin2 b/cbclp syncin1 syncin2 b/cbin1 b/cbin2 sogin1 sogin2 synctip clp cr offset (6) sub contrast (8) sub brightness (8) sub contrast (8) main contrast (8) v th (4) v hys (2) sub brightness (8) cb offset (6) sw g/yout sw b/cbout vrt vrt vrb vrb data mode rb7 to rb0 ra7 to ra0 gb7 to gb0 ga7 to ga0 bb7 to bb0 ba7 to ba0 xclk 1/2clk even/odd 1/2xclk dsync/divout clk sw sogt sw sogo sw sogp sw syncin top block diagram
5 CXA3516R amplifier block diagram clp clp drv gca clp pol 1bit 1bit 1bit r/crout r/crclp clpin rch r/crin1 r/crin2 sub contrast 8bit sub brightness 8bit clpoff sw vrt vrb adc r sw r sub brightness 8bit cr offset 6bit clp clp drv gca clp g/yout g/yclp gch rgb/yuv 1bit g/yin1 g/yin2 sub contrast 8bit sw vrt vrb adc g sw g sub brightness 8bit cb offset 6bit clp clp drv gca clp main contrast 8bit sync on green separator b/cbout b/cbclp bch b/cbin1 b/cbin2 sogin1 sogin2 v th 4bit v hys 2bit sub contrast 8bit sw vrt vrb adc b sync on green synct1 sync on green synct2 sync on green syncp sw b sw sogp sync tip clp sync tip clp sync sep sync sep sync sep amp power save 1bit sync sep power save 1bit dactest dactest out
6 CXA3516R peclin rc2 pll 1bit pd pol rc1 reset pulse generator ttlin sw m polarity ttlout ttlout ttlout dsync hold sw sw m m/s 1/2 sw div 1, 2, 4, 8 vco + 1/4 fine delay charge pump phase detector programmable counter ttlout ttlin ttlin ttlin polarity hold pol 1bit 1bit sog enable 1bit sog out pol sync out sw 1bit rgbin1/2sel 1bit 1bit iref clamp pulse xtload (ttl) syncp/hsync 1bit sync pol 3bit 12bit vco div hsync1/2 1bit clp pol 1bit ttlin dac polarity ttlin pll power save polarity polarity sw sw sw sw 6bit 1/256 to 1/4096 2bit 1bit dsync by-pass 1bit vco by-pass 2bit reset 1bit 1bit dsync hold clk enable div 1, 2, 4, 8 1bit 1bit 1bit xclk enable 1bit 1/2clk enable 1bit 1/2xclk enable unlock enable ttlout ttlout 1bit 1bit dsync enable even/odd (ttl) dsync/divout (ttl) clkin (pecl) xclkin (pecl) sogout (ttl) syncin1 (ttl) syncin2 (ttl) hold (ttl) clpin (ttl) sync on green synct1 sync on green synct2 sync on green syncp clk (ttl) xclk (ttl) 1/2clk (ttl) 1/2xclk (ttl) unlock 1/2clk (adc) clk (adc) dsync pol unlock detect j k q q m/s sw coarse delay coarse delay divout pulse width 2bit divout width 1bit divout delay divout delay pll block diagram
7 CXA3516R r/crin1 r1 g1 b1 h1 g/yin1 b/cbin1 sogin1 syncin1 r/crin2 r2 g2 b2 h2 g/yin2 b/cbin2 sogin2 syncin2 sync tip clamp sync sep sw sogt amp block synct1 synct2 synct pll block sw sogo pol ttl out sogout pll sync out sw 1bit sog out pol 1bit pedestal clamp pedestal clamp sync tip clamp sync sep sw pll sw syncin pol 1bit syncp/hsync 1bit hsync1/2 4bit v th 2bit v hys 1bit rgb in 1/2 select 1bit sync pol 1bit sog enable sw sogp sync sep syncp2 syncp1 sync block diagram
8 CXA3516R adc block diagram 8 ra7 to ra0 8 rb7 to rb0 8 ga7 to ga0 8 gb7 to gb0 8 ba7 to ba0 8 data format 3bit data inv 1bit bb7 to bb0 clk 1/2clk amp r amp g amp b vrb adc r adc g mode adc b clk cont vrb vrb vrb vrb vrt vrt vrt vrt adc power save 1bit vrt
9 CXA3516R pin description pin no. symbol i/o typical signal description 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16, 94 17 18, 92 19, 32, 42, 54, 65, 76, 90 20, 33, 44, 55, 67, 77, 89 21, 22, 24 to 28, 31 23, 30, 43, 50, 59, 66, 79, 86 29, 80 34 to 41 45 to 49, 51 to 53 56 to 58, 60 to 64 68 to 75 78, 81 to 85, 87, 88 91 93 95 b/cbout address r/crout nc nc xpower save dgndreg dv cc reg sda scl xsenable serout 3wire/i 2 c av cc adref av cc ad3 vrt dv cc ad3 dv cc adttl dgndadttl ra0 to ra7 dgndad3 agndad3 rb0 to rb7 ba0 to ba7 bb0 to bb7 ga0 to ga7 gb0 to gb7 dv cc ad vrb agndadref o i o i i i i o i o o o o o o o o 1.83v 1.83v ttl gnd 5v ttl ttl 5v 3.3v 2.9v 3.3v 5v gnd ttl gnd gnd ttl ttl ttl ttl ttl 5v 1.9v gnd amplifier output signal monitor i 2 c slave address setting amplifier output signal monitor not used not used power save setting register gnd register power supply control register data input control register clk input enable signal input for 3-wire control register 3-wire control register data readout selection of input between i 2 c bus and 3-wire bus reference power supply for a/d converter analog power supply for a/d converter top reference voltage output for a/d converter digital power supply for a/d converter ttl output power supply for a/d converter ttl output gnd for a/d converter data output for r-channel port a side digital gnd for a/d converter analog gnd for a/d converter data output for r-channel port b side data output for b-channel port a side data output for b-channel port b side data output for g-channel port a side data output for g-channel port b side digital power supply for a/d converter bottom reference voltage output for a/d converter reference voltage gnd for a/d converter
10 CXA3516R 96 97 98 99 100 101 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 123 124 125 126 127 128 129 130 132 133 dv cc pllttl dgndpllttl xclk clk 1/2xclk 1/2clk dsync/ divout unlock sogout hold xtload even/odd xclkin clkin syncin1 syncin2 clpin dv cc pll dgndpll av cc vco agndvco rc1 rc2 av cc ir iref agndir g/yin1 av cc ampg g/yin2 agndampg g/yclp b/cbclp r/crclp sogin1 b/cbin1 o o o o o o o i i i i i i i i i i i i i 5v gnd ttl ttl ttl ttl ttl open collector ttl ttl ttl ttl pecl pecl ttl ttl ttl 5v gnd 5v gnd 2.1v 2 to 4.5v 5v 1.2v gnd 5v gnd 2.8v ttl output power supply for pll ttl output gnd for pll inverted clk output clk output inverted 1/2clk output 1/2clk output dsync or divout signal output unlock signal output output for sync on green input for phase comparison disable signal programmable counter reset setting inverted pulse input of adc sampling clk inverted clk input for testing clk input for testing sync input 1 sync input 2 clamp pulse input digital power supply for pll digital gnd for pll analog power supply for pll vco analog gnd for pll vco external pin for pll loop filter external pin for pll loop filter analog power supply for iref current setup analog gnd for iref g/y signal input 1 power supply for g/y amplifier block g/y signal input 2 gnd for g/y amplifier block clamp capacitor for brightness clamp capacitor for brightness clamp capacitor for brightness sync on green signal input 1 b/cb signal input 1 pin no. symbol i/o typical signal description
11 CXA3516R 134 135 136 137 139 140 141 142 143 144 14, 102, 122, 131, 138 av cc ampb sogin2 b/cbin2 agndampb r/crin1 av cc ampr r/crin2 agndampr g/yout dac test out dpgnd i i i i o o 5v 2.8v gnd 5v gnd 1.83v 5v gnd power supply for b/cb amplifier block sync on green signal input 2 b/cb signal input 2 gnd for b/cb amplifier block r/cr signal input 1 power supply for r/cr amplifier block r/cr signal input 2 gnd for r/cr amplifier block monitor pin for amplifier output signal dac testing output for amplifier block control register gnd pin no. symbol i/o typical signal description
12 CXA3516R pin description and pin equivalent circuit pin no. symbol i/o typical signal equivalent circuit description power supply for amplifier block. gnd for amplifier block. sync separated sync signal output. separates and outputs the sync signal from sync on green input signal. (sync signal input from syncin1 and syncin2 pins can be output.) both positive and negative polarity outputs are supported. the polarity is selected by the control register. sync on green signal inputs. input via a 0.1f capacitor. when not used, connect to av cc . the sync tip clamp level is approximately 2.0v + vf (0.8v) = approximately 2.8v. at this time, if the pin voltage is lowered, these pins go to low impedance and current flows from the ic. when these pins are at the sync tip level or higher, the clamp circuit is off and only an input base current of approximately 1.2a flows. amplifier output signal monitor. each monitor can output either the entered signal immediately before a/d converter or the signal after switching between 2 types of input signals. the 2 types of input signals can be selected by the control register and output. these pins are emitter follower outputs, but the internal bias current is so small that a 820 ? resistor should be connected between these pins and gnd to monitor high frequency signals. when not used, connect to av cc amp. 3 r/crout o 1.83v 143 g/yout o 1.83v 1 b/cbout o 1.83v 105 sogout o ttl 132 sogin1 i 2.8v 135 sogin2 i 2.8v 140 125 134 142 127 137 av cc ampr av cc ampg av cc ampb agndampr agndampg agndampb 5v 5v 5v gnd gnd gnd 100 av cc amp agndamp 280 1 3 143 dgndpll 100k dv cc pll dv cc pllttl dgndpllttl 105 150 av cc ampg agndampg 100 132 135
13 CXA3516R amplifier block analog input signal. input via a 0.1f ceramic capacitor. the typical signal level is 0.7v. signals from 0.5v (min.) to 1.0v (max.) can be supported. in1 and in2 are selected by the control register. leave these pins open when not used. rgb input and ycbcr input can be selected by the control register. ? 1 the clamp level typical values are as follows. in case rgb is input 2.2v + vf (0.8v) = approximately 3v in case ycbcr is input g/yin: 2.2v + vf (0.8v) = approximately 3v r/crin, b/cbin: 2.7v + vf (0.8v) = approximately 3.5v clamp period: a clamp current of 1.2ma (max.) flows. signal period: a base current of 0.5a flows to the ic. 139 r/crin1 i ? 1 141 r/crin2 i ? 1 124 g/yin1 i ? 1 126 g/yin2 i ? 1 133 b/cbin1 i ? 1 136 b/cbin2 i ? 1 130 r/crclp ? 2 128 g/yclp ? 2 129 b/cbclp ? 2 clamp capacitor connector for brightness. connect 0.1f ceramic capacitors between these pins and gnd. ? 2 typical levels of the clamp are as follows. in case rgb is input sub brightness 00h: 2.68v 80h: 2.81v ffh: 2.94v in case ycbcr is input g/yclp is the same as above. r/cr, b/cbclp are as follows. cbcr offset 00h: 3.04v 20h: 3.07v 3fh: 3.102v clamp period: a clamp current of 1.2ma (max.) flows. signal period: a base current of 0.5a flows to the ic. av cc amp agndamp 400 100 500 100 25k 25k 250 100 124 126 133 136 139 141 av cc amp agndamp 100 100k 250 500 300 100 128 129 130 pin no. symbol i/o typical signal equivalent circuit description
14 CXA3516R clk output. output the same frequency clk as that of adc sampling. these are complemental ttl levels. these pins can be independently controlled on and off (power save) by the control register. 1/2clk output. output a half frequency clk of that of adc sampling. these are complemental ttl levels. these pins can be independently controlled on and off (power save) by the control register. data output for r-channel port a side. data output for r-channel port b side. data output for g-channel port a side. data output for g-channel port b side. data output for b-channel port a side. data output for b-channel port b side. 21, 22, 24 to 28, 31 34 to 41 68 to 75 78, 81 to 85, 87, 88 45 to 49, 51 to 53 56 to 58, 60 to 64 ra0 to ra7 rb0 to rb7 ga0 to ga7 gb0 to gb7 ba0 to ba7 bb0 to bb7 o o o o o o ttl ttl ttl ttl ttl ttl 15 95 16, 94 29, 80 18, 92 91 av cc adref agndadref av cc ad3 agndad3 dv cc ad3 dv cc ad 5v gnd 3.3v gnd 3.3v 5v reference power supply for a/d converter. reference gnd for a/d converter. analog power supply for a/d converter. analog gnd for a/d converter. digital power supply for a/d converter. digital power supply for a/d converter. clamp pulse input for the signal of analog input clamp and brightness clamp. both positive and negative polarity inputs are supported. the polarity is selected by the control register. the input pulse width should be 200ns or more. 1.5v 192 1.5k dv cc pll dgndpll 113 a/d converter block 113 clpin i 99 o ttl clk ttl 98 o xclk ttl 101 o 1/2clk ttl 100 o 1/2xclk ttl dgndpll 100k dv cc pllttl dgndpllttl 98 99 100 101 100k dv cc adttl dgndadttl dgndad3 pin no. symbol i/o typical signal equivalent circuit description
15 CXA3516R top reference voltage output for a/d converter input dynamic range. connect to av cc ad3 via a 1f ceramic capacitor. bottom reference voltage output for a/d converter input dynamic range. connect to av cc ad3 via a 1f ceramic capacitor. digital gnd for a/d converter. ttl output power supply for a/d converter. ttl output gnd for a/d converter. dgndad3 dv cc adttl dgndadttl gnd 5v gnd 23, 30, 43, 50, 59, 66, 79, 86 19, 32, 42, 54, 65, 76, 90 20, 33, 44, 55, 67, 77, 89 vrt o 2.9v 17 vrb o 1.9v 93 av cc adref agndadref 2k 20 90 17 av cc adref agndadref 4k 20 80 93 pin no. symbol i/o typical signal equivalent circuit description
16 CXA3516R pll block input sync signal at ttl level. the input polarity is switched by the control register. leave this pin open when not used. input sync signal at ttl level. the input polarity is switched by the control register. leave this pin open when not used. input signal for phase comparison hold. phase comparison is stopped, and vco oscillation frequency is held. when not be hold, fix the pin as follows. when holdpol register is "1", fix this pin to low level. when holdpol register is "0", leave this pin open or fix to high level. input the signal used to invert the a/d converter sampling clk. low: even mode high: odd mode normally fix it to low level. programmable counter reset. normally fix it to high level or leave open. in programmable counter test mode, set it to low level to call up the register contents. when not used, leave this pin open or fix to high level. 1.5v 192 40k dv cc pll dgndpll 112 111 107 108 106 dgndpll dv cc pll 14k 500 500 14k 110 109 clk input for adc operation check. input pecl level signal complementally. when using this pin, set clk to external input by the control register. leave this pin open when not used. syncin1 syncin2 hold even/odd xtload i i i i i ttl ttl ttl ttl ttl 111 112 106 108 107 110 109 clkin xclkin i i pecl pecl pin no. symbol i/o typical signal equivalent circuit description
17 CXA3516R this pin can output either dsync signal or divout signal. it can be selected by the control register. in addition, the output polarity can be selected by the control register. external pin for pll loop filter. external pin for pll loop filter. connect an external resistor (3k ? ) to supply a stabilized current to the inside of the ic. (charge pump current, etc.) connect this pin to gnd via 0.1f ceramic capacitor connected as close to the pin as possible. the band gap voltage is output. dsync/ divout o ttl 103 dgndpll 100k dv cc pll dv cc pllttl dgndpllttl 103 unlock signal output. make a discrimination between lock and unlock in the analog manner by connecting the external circuit. leave this pin open when not used. do not connect this pin to neither power supply nor gnd. unlock 104 rc1 2.1v 118 rc2 2 to 4.5v 119 iref i 1.2v 121 100k dgndpll dgndpllttl dv cc pllttl 104 av cc ir agndir dpgnd 118 119 dpgnd agndir av cc ir 121 114 115 96 dv cc pll dgndpll dv cc pllttl digital power supply for pll. digital gnd for pll. ttl output power supply for pll. 5v gnd 5v pin no. symbol i/o typical signal equivalent circuit description
18 CXA3516R input control register data. switching between the i 2 c and 3-wire bus mode is performed by the 3wire/i 2 c pin. control register block 9 i sda 9 dgndreg dv cc reg 200k 4k input control register clk. switching between the i 2 c and 3-wire bus mode is performed by the 3wire/i 2 c pin. 10 i scl 10 dgndreg dv cc reg 200k 4k 10k set slave address when using i 2 c bus mode. slave address: 1 0 0 1 1 s2 s1 0 connect this pin to gnd during 3-wire bus mode. 2 i add dgndreg dv cc reg 1k 15 15 15 2 97 120 123 116 117 dgndpllttl av cc ir agndir av cc vco agndvco ttl output gnd for pll. analog power supply for iref. analog gnd for iref. analog power supply for pll vco. analog gnd for pll vco. gnd 5v gnd 5v gnd v cc to 3/4v cc 3/4v cc to 2/4v cc 2/4v cc to 1/4v cc 1/4v cc to gnd 0 1 1 0 1 1 0 0 s2 s1 pin no. symbol i/o typical signal equivalent circuit description
19 CXA3516R when using the read mode of 3-wire bus mode, the register information written once is output in series order from the lsb of the setting sub address data. gnd for register. power supply for register. 7 8 gnd 5v dgndreg dv cc reg inputs enable signal for 3-wire bus. high level: control disabled low level: control enabled connect this pin to gnd when using i 2 c. xsenable i ttl 11 11 dgndreg dv cc reg 200k 4k selection of input between i 2 c bus and 3-wire bus. 3wire/i 2 c i 13 dgndreg dv cc reg 100k 100k 100k 15 15 13 serout o ttl 12 dgndreg dv cc reg 100k 12 xpower save i ttl 6 dgndreg dv cc reg 10 1k 6 v cc to 2/3v cc 2/3v cc to 1/3v cc 1/3v cc to gnd i 2 c 3v mode i 2 c 5v mode 3-wire bus mode power save for all functions including the control register block. high level: normal operation low level: power save pin no. symbol i/o typical signal equivalent circuit description
20 CXA3516R 14, 102, 122, 131, 138 4 5 dpgnd nc nc gnd this pin is connected to the die pad. connect to the specified gnd in application circuit. not used. leave this pin open or connect to gnd. not used. leave this pin open or connect to gnd. dac test output for control register of amplifier block. current is output by open collector. normally connect to av cc . dac test out o 5v 144 dgndreg dv cc reg 144 pin no. symbol i/o typical signal equivalent circuit description
21 CXA3516R electrical characteristics (ta = 25 c, av cc , dv cc = 5v, av cc 3, dv cc 3 = 3.3v) supply current current during operating 5v current consumption 3.3v current consumption register control power save current 5v power save current consumption 3.3v power save current consumption xpower save pin control power save current 5v power save current consumption 3.3v power save current consumption clk = dc clk = dc 180 180 26 3.0 9.0 3.0 240 226 42 7.2 22 7.2 ma ma ma ma ma ma i cc 5 i cc 3 i cc 5ps i cc 3ps i cc 5xps i cc 3xps 3-wire control bus (sda, scl, senable) high level input voltage low level input voltage high level input current low level input current threshold voltage high low threshold voltage low high input capacitance scl clock frequency xsenable setup time xsenable hold time xsenable high level pulse width sda setup time sda hold time sda delay time in write/read mode in write/read mode in write/read mode in write/read mode in write/read mode in write/read mode in read mode 2.0 0 2.0 5.0 3 0 300 3 0 1.3 1.65 10 10 10 10 11 5.0 0.8 0 0 10 10 v v a a v v pf mhz ns ns ns ns ns ns v ih v il i ih i il v thhl1 v thlh1 c i f scl1 t ens t enh t enpw t ds t dh t d register item symbol measurement conditions min. typ. max. unit item symbol measurement conditions min. typ. max. unit
22 CXA3516R i 2 c control bus (sda, scl) high level input voltage low level input voltage high level input current low level input current threshold voltage high low threshold voltage low high high level input voltage low level input voltage high level input current low level input current threshold voltage high low threshold voltage low high sda low level output voltage input capacitance scl clock frequency bus free-time stop start hold time (resend) hold time in scl clock at low state hold time in scl clock at high state setup time under resend start condition data hold time data setup time rise time fall time setup time under stop condition capacitive load of each bus line i oh = 3ma start condition: after this period, first clock is generated. 2.3 0 2.0 5.0 2.0 0 1.0 5.0 0 0 4.7 4.0 4.7 4.0 4.7 0 250 4.0 1.6 1.95 1.3 1.65 0.15 50 5.0 5.0 5.0 5.0 5.0 5.0 5000 5.0 5.0 1.0 0 0 5.0 0.8 0 0 0.5 10 100 1000 300 400 v v a a v v v v a a v v v pf khz s s s s s s ns ns ns s pf v ih v il i ih i il v thhl2 v thlh2 v ih v il i ih i il v thhl3 v thlh3 v ol c i f scl2 t buf t hd;sta t low t high t su;sta t hd;dat t su;dat t r t f t su;sto cb register (cont.) i 2 c (high) mode i 2 c (low) mode item symbol measurement conditions min. typ. max. unit
23 CXA3516R brightness characteristics brightness level h (adc out) brightness level l brightness level m brightness level h brightness level low side variable range brightness level high side variable range clamp characteristics cb, cr clamp level m (adc out) cb, cr clamp level l cb, cr clamp level m cb, cr clamp level h cb, cr clamp level low side variable range cb, cr clamp level high side variable range clamp pulse minimum width contrast characteristics main contrast control l main contrast control m main contrast control h sub contrast control l sub brightness g, b, r = 255 adc output conversion level sub brightness g, b, r = 0 g, b, r out pin voltage sub brightness g, b, r = 128 g, b, r out pin voltage sub brightness g, b, r = 255 g, b, r out pin voltage v brl v brm v brh v brm cb, cr offset = 32 adc output conversion level cb, cr offset = 0 b, r out pin voltage cb, cr offset = 32 b, r out pin voltage cb, cr offset = 63 b, r out pin voltage v cll v clm v clh v clm main contrast = 0 sub contrast = 128 vin = 1.2vp-p rgb/yuv mode, g, b, r out main contrast = 128 sub contrast = 128 vin = 0.6vp-p rgb/yuv mode, g, b, r out main contrast = 255 sub contrast = 128 vin = 0.45vp-p rgb/yuv mode, g, b, r out main contrast = 128 sub contrast = 0 vin = 0.85vp-p rgb/yuv mode, g, b, r out 53 1.388 1.63 1.86 120 1.94 1.99 2.03 200 0.62 1.23 1.79 0.96 61 1.588 1.83 2.06 242 230 128 2.23 2.28 2.34 60 60 0.78 1.53 2.24 1.2 69 1.788 2.03 2.26 136 2.46 2.51 2.58 0.94 1.84 2.69 1.44 lsb v v v mv mv lsb v v v mv mv ns times times times times v brhad v brl v brm v brh v clmad v cll v clm v clh t wclp v mcl v mcm v mch v scl amp item symbol measurement conditions min. typ. max. unit
24 CXA3516R sub contrast control h gain difference among rgb frequency response cross talk characteristics cross talk between channels cross talk among rgb main contrast = 128 sub contrast = 255 vin = 0.55vp-p rgb/yuv mode, g, b, r out main contrast = 128 sub contrast = 128 vin = 0.6vp-p rgb/yuv mode, g, b, r out main contrast = 128 sub contrast = 128 vin = 0.6vp-p rgb/yuv mode, g, b, r out main contrast = 128 sub contrast = 128 fin = 100mhz, vin = 0.6vp-p main contrast = 128 sub contrast = 128 fin = 100mhz, vin = 0.6vp-p 1.48 8 1.85 0 220 35 30 2.22 8 times % mhz db db v sch ? gain fc 3db ctc ctb amp (cont.) sync sep input characteristics sync tip input minimum amplitude sync tip input minimum duty sync sep threshold voltage sync sep hysteresis voltage sync sep v th = 1000 sync sep v hys = 10 sync sep v th = 1000 sync sep v hys = 10 0.2 5 116 36 145 45 174 54 vp-p % mv mv v syn d syn v th v hys syncsep item symbol measurement conditions min. typ. max. unit item symbol measurement conditions min. typ. max. unit
25 CXA3516R hold characteristics rc1 pin leak current sync signal input characteristics sync signal input frequency range vco characteristics clock frequency clock frequency clock frequency clock frequency vco lock range vco gain 1 vco gain 2 vco gain 3 vco gain 4 jitter characteristics sync input signal clock output jitter (ntsc) sync input signal clock output jitter (vga) sync input signal clock output jitter (svga) sync input signal clock output jitter (xga) sync input signal clock output jitter (sxga) sync input signal clock output jitter (uxga) delay sync clock output jitter vco frequency divider div = 1/1 vco frequency divider div = 1/2 vco frequency divider div = 1/4 vco frequency divider div = 1/8 vco frequency divider div = 1/1 vco frequency divider div = 1/2 vco frequency divider div = 1/4 vco frequency divider div = 1/8 triggered at sync fsync = 15.73khz fclk = 12.27mhz n = 780 triggered at sync fsync = 31.47khz fclk = 25.18mhz n = 800 triggered at sync fsync = 48.08khz fclk = 50.00mhz n = 1040 triggered at sync fsync = 56.48khz fclk = 75.00mhz n = 1328 triggered at sync fsync = 79.98khz fclk = 135.01mhz n = 1688 triggered at sync fsync = 75.00khz fclk = 162.00mhz n = 2160 triggered at dsync 10 80 40 14 5 2.0 300 150 75 37.5 2.4 1.6 1.3 0.9 0.8 0.8 2.7 1.8 1.4 1.0 0.9 0.85 1.0 130 165 80 40 14 4.5 500 250 125 62.5 3 2.0 1.5 1.1 1.0 1.0 0.1 na khz mhz mhz mhz mhz v mrad/sv mrad/sv mrad/sv mrad/sv ns ns ns ns ns ns ns ileak f sync fclk1 fclk2 fclk3 fclk4 vlock kvco1 kvco2 kvco3 kvco4 tj1p-p tj2p-p tj3p-p tj4p-p tj5p-p tj6p-p tj7p-p pll item symbol measurement conditions min. typ. max. unit
26 CXA3516R resolution dc characteristics integral linearity error differential linearity error reference voltage top reference voltage bottom reference voltage input dynamic range ac characteristics maximum conversion frequency of straight data out mode maximum conversion frequency of dmux parallel data out mode maximum conversion frequency of dmux interleaved data out mode maximum conversion frequency of 4:2:2 data out d2 mode maximum conversion frequency of 4:2:2 data out special mode avccad3 as a reference avccad3 as a reference vrt vrb 0.3 1.3 0.9 100 165 165 100 100 8 1.0 0.4 0.4 1.4 1.0 0.7 0.6 1.6 1.1 bit lsb lsb v v v msps msps msps msps msps ile dle vrt vrb vtb fc fc fc fc fc adc item symbol measurement conditions min. typ. max. unit
27 CXA3516R digital input (pecl) digital input voltage: h digital input voltage: l digital input current: h digital input current: l digital input (ttl) digital input voltage: h digital input voltage: l threshold voltage digital input current: h digital input current: l digital output (ttl) digital output voltage: h digital output voltage: l dvccpll as a reference dvccpll as a reference v ih1 = dv cc pll 0.8v v il1 = dv cc pll 1.6v v ih = 3.5v v il = 0.2v i oh = 2ma i oh = 2ma i oh = 2ma i oh = 2ma i ol = 1ma 1.15 100 200 2.0 10 20 2.4 2.3 2.05 1.85 1.5 2.95 2.7 2.45 2.2 0.2 1.5 100 0 0.8 5 0 3.3 3.0 2.75 2.5 0.5 v v a a v v v a a v v v v v v ih1 v il1 i ih1 i il1 v ih2 v il2 v th i ih2 i il2 v oh1 v oh2 v oh3 v oh4 v ol i/o item symbol measurement conditions min. typ. max. unit
28 CXA3516R clock output rise time clock output fall time delay sync output rise time delay sync output fall time data output rise time data output fall time hold signal setup time hold signal hold time delay sync delay time coarse delay delay sync delay time fine delay clock output delay from sync input signal delay time between clock output and dsync/divout signal divout signal output delay time clock 1/2 clock 1/2 clock data clock data 0.8 to 2.0v (clk, 1/2clk) 2.0 to 0.8v (clk, 1/2clk) 0.8 to 2.0v (dsync, divout, sogout) 2.0 to 0.8v (dsync, divout, sogout) 0.8 to 2.0v 2.0 to 0.8v cl = 9pf cl = 9pf difference between delay sync signal and divout signal 0.8 1.0 0.8 1.0 0.9 0.9 20 20 3 1/32 6.0 0.8 4 0.9 2.3 2.2 1.4 1.5 1.4 1.5 1.2 1.2 7.0 1.0 1.2 2.6 2.8 2.3 2.8 2.3 2.8 2.0 2.0 6 64/32 8.0 1.3 5 1.6 3.2 3.8 ns ns ns ns ns ns ns ns clk clk ns ns clk ns ns ns t r_clk t f_clk t r_dsync t f_dsync t r_data t f_data ths thh td_1 td_2 td_3 td_4 td_5 td_6 td_7 td_8 item symbol measurement conditions min. typ. max. unit timing characteristics
29 CXA3516R electrical characteristics measurement circuit (3-wire control) 0.1 75 820 0.1 75 0.1 75 0.1 75 0.1 75 0.1 1 100p 0.33 3.3k 3k 330p 75 5k 0.1 0.1 4.7k 4.7k 820 820 av cc 5v dv cc 5v 3.3v dgnd agnd 1 analog signal analog signal analog signal bus controler 37 a a a 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 1 2 3 4 121 122 123 124 125 126 127 128 129 130 131 132 142 143 144 110 109 111 112 113 114 115 116 117 118 119 120 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 36 11 21 31 b/cbout address r/crout nc nc xpower save dgndreg dv cc reg sda scl xsenable serout 3wire/i 2 c dpgnd av cc adref av cc ad3 vrt dv cc ad3 dv cc adttl dgndadttl ra0 ra1 dgndad3 ra2 ra3 ra4 ra5 ra6 agndad3 dgndad3 ra7 dv cc adttl dgndadttl rb0 rb1 rb2 ga4 ga3 ga2 ga1 ga0 dgndadttl dgndad3 dv cc adttl bb7 bb6 bb5 bb4 bb3 gndad3 bb2 bb1 bb0 dgndadttl dv cc adttl ba7 ba6 ba5 dgndad3 ba4 ba3 ba2 ba1 ba0 dgndadttl dgndad3 dv cc adttl rb7 rb6 rb5 rb4 rb3 even/odd xtload hold sogout unlock dsync/divout dpgnd 1/2clk 1/2xclk clk xclk dgndpllttl dv cc pllttl agndadref av cc ad3 vrb dv cc ad3 dv cc ad dv cc adttl dgndadttl gb7 gb6 dgndad3 gb5 gb4 gb3 gb2 gb1 agndad3 dgndad3 gb0 dgndadttl dv cc adttl ga7 ga6 ga5 xclkin clkin syncin1 syncin2 clpin dv cc pll dgndpll av cc vco agndvco rc1 rc2 av cc ir iref dpgnd agndir g/yin1 av cc ampg g/yin2 agndampg g/yclp b/cbclp r/crclp dpgnd sogin1 b/cbin1 av cc ampb sogin2 b/cbin2 agndampb dpgnd r/crin1 av cc ampr r/crin2 agndampr g/yout dactestout clamp pulse hsync ext clk ext xclk
30 CXA3516R control register functions table block function feedback programmable counter control vco frequency divider control delay control (lower order) delay control (higher order) charge pump current control divout signal pulse width control divout signal delay control delay sync output polarity control hold input polarity control 12 2 6 2 3 2 1 1 1 0 1 1 2 2 3 3 3 4 4 m4 o m3 o m2 o o o m1 o o o m0 m8 o o n2 m7 o o n1 m6 o o o n0 m5 o o o vco div div1, 2, 4, 8 fine delay coarse delay charge.pump divout width divout delay dsync pol hold pol frequency division ratio = (m + 1) 8 + n 00: 1/1 01: 1/2 10: 1/4 11: 1/8 000000: 1/32clk 111111: 64/32clk 00: 3clk 01: 4clk 10: 5clk 11: 6clk 000: 100a 001: 200a 010: 300a 011: 400a 100: 500a 101: 600a 110: 700a 111: 800a 00: 1clk 01: 2clk 10: 4clk 11: 8clk 0: 4clk 1: 5clk 0: negative 1: positive 0: negative 1: positive bit register no. pll pll pll pll pll pll pll pll pll data d7 d6 d5 d4 d3 d2 d1 d0 register name control range (typ.)
31 CXA3516R block function phase comparison input positive/negative control sync input polarity control sog out polarity control clamp pulse input polarity control external clock/internal vco switching delay sync output/divout switching delay sync hold function output sog/hsync switching hsync1, 2 input/soga switching hsync1 input/hsync2 input switching ttl output off function (clock) ttl output off function (inverse clock) ttl output off function (1/2 clock) ttl output off function (inverse 1/2 clock) ttl output off function (delay sync) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4 5 5 5 5 5 5 6 6 6 6 6 o o o o o o o o o o o o o o o pd pol sync pol sog out pol clp pol vco by-pass dsync by-pass dsync hold sync out sw syncp/ hsync hsync 1/2 clk enable xclk enable 1/2clk enable 1/2xclk enable dsync enable 0: negative 1: positive 0: negative 1: positive 0: negative 1: positive 0: negative 1: positive 0: ext clk 1: int vco 0: divout 1: dsync 0: normal 1: hold 0: synct 1: syncp/hsync 0: syncp 1: hsync1, 2 0: ext sync1 1: ext sync2 0: ttl out off 1: ttl out on 0: ttl out off 1: ttl out on 0: ttl out off 1: ttl out on 0: ttl out off 1: ttl out on 0: ttl out off 1: ttl out on bit register no. pll pll pll pll pll pll pll pll pll pll pll pll pll pll pll data d7 d6 d5 d4 d3 d2 d1 d0 register name control range (typ.)
32 CXA3516R block function ttl output off function (unlock) ttl output off function (sog out) ttl output off function (ser out) main contrast sub contrast gch sub contrast bch sub contrast rch sub brightness gch sub brightness bch sub brightness rch cb input clamp level adjustment in yuv mode cr input clamp level adjustment in yuv mode ycbcr input mode clamp level switching rgb out output signal selection sw output and amp output rgb2 input selection 1 1 1 8 8 8 8 8 8 8 6 6 1 1 1 6 6 6 7 8 9 10 11 12 13 14 15 16 16 16 o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o unlock enable sog enable serout enable main contrast sub contrast g sub contrast b sub contrast r sub brightness g sub brightness b sub brightness r cb offset cr offset ycbcr mode rgb out select rgb in select 0: ttl out off 1: ttl out on 0: ttl out off 1: ttl out on 0: ttl out off 1: ttl out on 00000000: mgain = 0.78 11111111: mgain = 2.24 00000000: mgain = 0.79 11111111: mgain = 1.21 00000000: mgain = 0.79 11111111: mgain = 1.21 00000000: mgain = 0.79 11111111: mgain = 1.21 00000000: vrb 61lsb 11111111: vrb + 61lsb 00000000: vrb 61lsb 11111111: vrb + 61lsb 00000000: vrb 61lsb 11111111: vrb + 61lsb 00000000: 128lsb 16lsb 11111111: 128lsb + 16lsb 00000000: 128lsb 16lsb 11111111: 128lsb + 16lsb 0: rgb in 1: ycbcr in 0: amp out 1: sw out 0: in1 1: in2 bit register no. pll pll register amp amp amp amp amp amp amp amp amp amp amp amp data d7 d6 d5 d4 d3 d2 d1 d0 register name control range (typ.)
33 CXA3516R block function brightness clamp off sync sep hysteresis level setting during sync on green sync sep threshold level setting during sync on green adc data output polarity control data output mode switching adc power save amp power save pll power save sync sep power save ttlout clp level 1 2 4 1 3 1 1 1 1 2 16 17 17 18 18 19 19 19 19 19 o o o o o o o o o o o o o o o o o brightness clp sync sep v hys sync sep v th data out pol data out mode adc power save amp power save pll power save sync sep power save ttlout clp 0: on 1: off 00: 2mv 01: 20mv 10: 45mv 11: 70mv 0000: 75mv 10mv step 1111: 215mv 0: all 1 all 0(negative) 1: all 0 all 1(positive) 000: straight 001: dmux parallel 010: dmux interleaved 011: yuv4:2:2 d2 111: yuv4:2:2 special 0: active 1: power save 0: active 1: power save 0: active 1: power save 0: active 1: power save 00: 2.20v 01: 2.45v 10: 2.70v 11: 2.95v bit register name control range (typ.) register no. amp sync sep sync sep adc adc adc amp pll sync sep ttlout d7 d6 d5 d4 d3 d2 d1 d0 data
34 CXA3516R register no. register name d7 data d6 d5 d4 d3 d2 d1 d0 sub address register 0 register 1 register 2 register 3 register 4 register 5 register 6 register 7 register 8 register 9 register 10 vcodiv1 reference vcodiv2 reference delay reference cp reference polarity reference sync reference ttlout enable reference main contrast reference sub contrast g reference sub contrast b reference sub contrast r reference vcodiv bit7 0 coarse delay bit1 0 serout enable 1 main contrast bit7 1 sub contrast g bit7 1 sub contrast b bit7 1 sub contrast r bit7 1 vcodiv bit6 0 coarse delay bit0 0 sog enable 1 main contrast bit6 0 sub contrast g bit6 0 sub contrast b bit6 0 sub contrast r bit6 0 vcodiv bit5 1 div1, 2, 4, 8 bit1 0 fine delay bit5 1 divout delay 1 clp pol 1 hsync1/2 0 unlock enable 1 main contrast bit5 0 sub contrast g bit5 0 sub contrast b bit5 0 sub contrast r bit5 0 vcodiv bit4 1 div1, 2, 4, 8 bit0 1 fine delay bit4 0 divout width bit1 0 sogout pol 1 syncp/ hsync in 1 dsync enable 1 main contrast bit4 0 sub contrast g bit4 0 sub contrast b bit4 0 sub contrast r bit4 0 vcodiv bit3 1 vcodiv bit11 0 fine delay bit3 0 divout width bit0 0 sync in pol 1 sync out sw 1 1/2xclk enable 1 main contrast bit3 0 sub contrast g bit3 0 sub contrast b bit3 0 sub contrast r bit3 0 vcodiv bit2 0 vcodiv bit10 1 fine delay bit2 0 charge pump bit2 0 pd pol 1 dsync hold 0 1/2clk enable 1 main contrast bit2 0 sub contrast g bit2 0 sub contrast b bit2 0 sub contrast r bit2 0 vcodiv bit1 0 vcodiv bit9 0 fine delay bit1 0 charge pump bit1 1 hold pol 1 dsync by-pass 1 xclk enable 1 main contrast bit1 0 sub contrast g bit1 0 sub contrast b bit1 0 sub contrast r bit1 0 vcodiv bit0 0 vcodiv bit8 1 fine delay bit0 0 charge pump bit0 1 dsync pol 1 vco by-pass 1 clk enable 1 main contrast bit0 0 sub contrast g bit0 0 sub contrast b bit0 0 sub contrast r bit0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 00 (h) 01 (h) 02 (h) 03 (h) 04 (h) 05 (h) 06 (h) 07 (h) 08 (h) 09 (h) 0a (h) 38 (h) 15 (h) 20 (h) 23 (h) 3f (h) 1b (h) ff (h) 80 (h) 80 (h) 80 (h) 80 (h) register assignment pll amp a4 a3 a2 a1 a0 hex code hex code
35 CXA3516R register no. register name d7 d6 d5 d4 d3 d2 d1 d0 data a4 a3 sub address a2 a1 a0 hex code hex code register 11 register 12 register 13 register 14 register 15 register 16 register 17 register 18 register 19 sub brightness g reference sub brightness b reference sub brightness r reference cboffset reference croffset reference amp mode reference syncsep reference output mode reference power save reference sub brightness g bit7 1 sub brightness b bit7 1 sub brightness r bit7 1 sub brightness g bit6 0 sub brightness b bit6 0 sub brightness r bit6 0 sub brightness g bit5 0 sub brightness b bit5 0 sub brightness r bit5 0 cb offset bit5 1 cr offset bit5 1 sync sep v th bit3 1 ttlout clp bit1 1 sub brightness g bit4 0 sub brightness b bit4 0 sub brightness r bit4 0 cb offset bit4 0 cr offset bit4 0 sync sep v th bit2 0 ttlout clp bit0 1 sub brightness g bit3 0 sub brightness b bit3 0 sub brightness r bit3 0 cb offset bit3 0 cr offset bit3 0 brightness clp 0 sync sep v th bit1 0 data out mode bit2 0 sync sep power save 0 sub brightness g bit2 0 sub brightness b bit2 0 sub brightness r bit2 0 cb offset bit2 0 cr offset bit2 0 rgb in1/2 select 0 sync sep v th bit0 0 data out mode bit1 0 pll power save 0 sub brightness g bit1 0 sub brightness b bit1 0 sub brightness r bit1 0 cb offset bit1 0 cr offset bit1 0 rgb out select 0 sync sep v hys bit1 1 data out mode bit0 1 amp power save 0 sub brightness g bit0 0 sub brightness b bit0 0 sub brightness r bit0 0 cb offset bit0 0 cr offset bit0 0 ycbcr mode 0 sync sep v hys bit0 0 data out pol 1 adc power save 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0b (h) 0c (h) 0d (h) 0e (h) 0f (h) 10 (h) 11 (h) 12 (h) 13 (h) 80 (h) 80 (h) 80 (h) 20 (h) 20 (h) 00 (h) 22 (h) 03 (h) 30 (h) amp sync sep adc power save
36 CXA3516R description of operation control register programmable control can be performed for many functions of this ic. 1) mode selection both i 2 c bus and 3-wire bus mode can be supported, and either of these modes can be selected by the 3wire/i 2 c (pin 13). 3wire/i 2 c pin voltage setting mode 0v 1/2v cc v cc (5v) i 2 c (high) i 2 c (low) 3-wire bus i 2 c (high) mode threshold voltage (low high) threshold voltage (high low) 1.95v 1.6v i 2 c (low) mode threshold voltage (low high) threshold voltage (high low) 1.65v 1.3v 3-wire bus mode threshold voltage (low high) threshold voltage (high low) 1.65v 1.3v the pin threshold voltages are set at 1/3v cc and 2/3v cc . 2) threshold voltage in i 2 c bus mode, both sda (pin 9) and scl (pin 10) are input. these input logic signals can have two threshold voltages by the 3-wire/i 2 c. these threshold voltages have the following hysteresis. sda, scl pin threshold voltages sda, scl and xsenable pin threshold voltages in 3-wire bus mode, the threshold voltages of the logic signal input to the sda, scl and xsenable pins have the following hysteresis.
37 CXA3516R 3-wire bus mode various control can be performed by setting the internal control register values via the serial interface comprised of the three pins sda (pin 9), scl (pin 10) and xsenable (pin 11). data can be accepted when xsenable is low level. when xsenable is high level, data cannot be accepted. the sda pins of multiple ic can also be connected to the same bus line and each ic can be controlled independently by xsenable. xsenable may change the state when scl is high level. 1) write mode 8-bit control data consisting of a 7-bit sub address and 1-bit read/write setting is input in series from the lsb to the sda pin. when read/write setting is "1", data can be written to register. when this ic is used in 3-wire bus mode, the sub address is 5 bits, so always set the 2 msb bits to "0". input the clock to the scl pin. data is loaded to the sda pin at the rising edge of this clock. the data is set in the register at the rising edge of xsenable. the sda and scl pins are also used in i 2 c bus control mode. xsenable scl sda a0 lsb sub address msb lsb msb a1 a2 a3 a4 a5 a6 00 1 d0d1d2d3d4d5d6d7 data read/write xsenable scl sda t ens t ds t dh t enh t enpw read/write 0: read mode 1: write mode set the vco post-stage frequency divider (div1, 2, 4, 8) and programmable counter (vcodiv) in the following order. the data is set when register1 is sent. register0 (sub address (h): 00) register1 (sub address (h): 01)
38 CXA3516R 2) read mode input the 7-bit sub address and 1-bit read/write setting to the sda pin. when read/write setting is "0", the 8-bit internally set data is output in series from the lsb by the serout (pin 12). while data is being output from the serout pin, don't care what data is input to the sda pin. use the read function to check whether the data is set correctly inside the ic. a5 a6 00 xsenable scl sda serout a0 lsb sub address msb lsb msb a1 a2 a3 a4 0 d0 d1 d2 d3 d4 d5 d6 d7 data xsenable scl sda serout t ens t ds t dh t d t enh read/write t enpw read/write 0: read mode 1: write mode the serout pin is ttl output. when not using the readout function, the ttl output circuit can be turned off by control register. register: serout enable serout output status 0 function off 1 function on power-on reset when the power supply rises, the power-on reset circuit operates and all the control register data is set to "1". amp, adc, pll and syncsep are all set to power save mode, and all the ttl output pins are set to high impedance mode. therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes.
39 CXA3516R i 2 c bus mode various control can be performed by setting the internal control register values via the serial interface comprised of the sda (pin 9) and scl (pin 10). this mode has only a write mode for setting data, and there is no read mode. therefore, address "s0" set read/write is always "0". address pin voltage slave address 0v 1001 1000 1/3v cc 1001 1100 2/3v cc 1001 1110 v cc (5v) 1001 1010 slave address s7 1 s6 0 s5 0 s4 1 s3 1 s2 x s1 x s0 0 the pin threshold voltages are set to 1/4v cc , 1/2v cc and 3/4v cc . an 8-bit slave address (ic address), 8-bit sub address, and a number of 8-bit data strings are input in series from the msb to the sda pin. when this ic is used in i 2 c bus mode, sub address is 5 bits, and 3 bits of msb side are set to always "0". ack signal is returned from the ic to confirm that the data has been received for each 8-bit data. the sub address can be designated optionally. the sub address is auto-incremented in order from the designated sub address, and the data strings are loaded in succession. to set the data at a specific separated sub address, either send the stop condition and then reset the sub address, or also send the data of unchanged portions so that the data is continuous. only auto-increment mode is supported, and the sub address + data + sub address + data mode where only specific sub addresses are designated is not supported. s7 sda s6 s5 s4 s3 s2 s1 s0 msb lsb a6 a7 a5 0 00 a4 sub address a3 a2 a1 a0 ack ack slave address d6 d7 d5 d4 data d3 d2 d1 d0 ack d6 d7 d5 d4 data d3 d2 d1 d0 ack scl stop condition start condition start condition when scl pin is high level, the signal input to sda pin has a falling edge, there is start condition. stop condition when scl pin is high level, the signal input to sda pin has a rising edge, there is stop condition. four different kinds of slave address (ic address) can be set by externally setting the address (pin 2) to a specific voltage.
40 CXA3516R i 2 c bus control signals sda scl p s sr p t buf t low t r_reg t f_reg t hd;sta t hd;sta t hd;dat t su;dat t su;sta t su;sto t high power-on reset when the power supply rises, the power-on reset circuit operates and all the control register data are set to "1". amp, adc, pll and syncsep are all set to power save mode, and all the ttl output pins are set to high impedance mode. therefore, it is possible to share the same bus interface with other digital outputs having high impedance modes.
41 CXA3516R amplifier this is a 3-channel amp that optimizes the ac coupled rgb analog input signals and ycbcr analog input signals for adc input. switch input mode between rgb input or ycbcr input with the control register. the ac coupled analog input signals are synchronously clamped by the externally input clamp pulse at a pedestal level. an input capacitor of 0.1f is recommended. allowing two lines of input to be selected for the analog input signal, the amp includes a high frequency, low cross talk video switch circuit for input switching. switching is performed using a control register. when using only one line, leave the unused line open. the input band of the analog input signal is 220mhz in the 3db bandwidth range. there are main contrast and sub-contrast of the gain used to adjust the analog input signal to full scale (1v typ.) of the adc. each can be adjusted to one of 256 levels using control registers. main contrast is controlled by moving the gain of the 3 rgb channels. the each gain of the 3 rgb channels can be controlled independently. in rgb input mode, the clamp level used for the black level adjustment can be adjusted independently for the 3 channels to any of 256 levels by using sub-brightness. the ? clp pin ? 1 is connected to the hold capacitor of the clamp circuit for the sub-brightness. a hold capacitor of 0.1f is recommended. the ? out pins ? 2 can output signal immediately before input to the adc or the signal after switching between the two lines of input select switch. either of them can be selected by control register. as for emitter follower output, since the internal bias current is small, be sure to connect an 820 ? resistor between the ? out pins ? 2 and agnd in order to view the signal with a high frequency. a 75 ? driver cannot be supported. in addition, load capacitance should be 5pf or less. when the sync on green signal is monitored at the ? out pins ? 2 after the two lines of select switch, the sync amplitude is a maximum of 0.3v, for a limiter is applied at the amplifier input stage. in ycbcr signal input mode, y can be adjusted to any of 256 levels using the sub-brightness while cb and cr can be adjusted to any of 64 levels using the cb or cr offset. a detailed description of the above registers is given below. ? 1 ? clp pins: overall naming for r/cr clp (pin 130), g/y clp (pin 128), b/cb clp (pin 129) ? 2 ? out pins: overall naming for r/cr out (pin 3), g/y out (pin 143), and b/cb out (pin 1) analog input signal mode switching analog input signal supports both rgb analog input signal and ycbcr analog input signal. this register switches the clamp level of the input clamp block and the amplifier output block in each mode. however, the g/ych perform the same processing in both rgb input mode and ycbcr input mode. register: ycbcr mode analog input signal mode 0 rgb input 1 ycbcr input register: rgb in select analog input signal channel switching 0 in1 1 in2 input channel switching input supports 2-channel input, and the input can be selected by an internal switch. register: clp pol clamp pulse polarity 0 negative 1 positive clamp pulse input polarity the clamp pulse input polarity can be selected by an internal switch.
42 CXA3516R register: brightness clp clamp operation 0 clamp operation 1 clamp off brightness clamp off function clamp operation can be set to a mode where only the post-stage brightness clamp does not operate even if a clamp pulse is input to the clpin (pin 113). at this time, all three channels of the ? clp pins ? 1 are set to high impedance simultaneously, and the signal black level can be varied in an analog manner by setting the voltages externally. however, the voltage value set here is not related to the vrt (pin 17) and vrb (pin 93) voltages or the ? out ? 2 monitor signal output dc levels. therefore the value should be set while monitoring the adc data output or the data after that. register: rgb out select monitor output switching 0 amplifier output 1 switch output monitor signal output selection the two monitor signal outputs ( ? out pins ? 2 ) of the amplifier can be selected by an internal switch. one is amplifier output signal immediately before input to the adc, and other is after switching between the two lines of select switch. register: main contrast amplifier gain (typ.) sub contrast = 128 0 0.78 128 1.53 255 2.24 main contrast the rgb channel gains can be set collectively by an 8-bit dac setting. register: sub contrast r rch gain adjustment (typ.) 0 21% 128 0% 255 +21% rch sub contrast the rch contrast (r amplifier gain) can be adjusted independently within the range of 21% relative to the main contrast by an 8-bit dac setting. register: sub contrast g gch gain adjustment (typ.) 0 21% 128 0% 255 +21% gch sub contrast the gch contrast (g amplifier gain) can be adjusted independently within the range of 21% relative to the main contrast by an 8-bit dac setting. register: sub contrast b bch gain adjustment (typ.) 0 21% 128 0% 255 +21% bch sub contrast the bch contrast (b amplifier gain) can be adjusted independently within the range of 21% relative to the main contrast by an 8-bit dac setting.
43 CXA3516R register: ycbcr mode input signal mode 0 rgb register: sub brightness r level shift amount (typ.) 0 61lsb 128 0lsb 255 +61lsb rch sub brightness in rgb mode the rch sub brightness (black level voltage) can be set by an 8-bit dac during rgb signal input. the rch sub brightness can be varied within the range of 25% of the adc input dynamic range (approximately 1v) centering on vrb (pin 93) (approximately 1.9v). register: ycbcr mode input signal mode 0 rgb register: sub brightness g level shift amount (typ.) 0 61lsb 128 0lsb 255 +61lsb gch sub brightness in rgb mode the gch sub brightness (black level voltage) can be set by an 8-bit dac during rgb signal input. the gch sub brightness can be varied within the range of 25% of the adc input dynamic range (approximately 1v) centering on vrb (pin 93) (approximately 1.9v). register: ycbcr mode input signal mode 0 rgb register: sub brightness b level shift amount (typ.) 0 61lsb 128 0lsb 255 +61lsb bch sub brightness in rgb mode the bch sub brightness (black level voltage) can be set by an 8-bit dac during rgb signal input. the bch sub brightness can be varied within the range of 25% of the adc input dynamic range (approximately 1v) centering on vrb (pin 93) (approximately 1.9v). register: ycbcr mode input signal mode 1 ycbcr register: cb offset level shift amount (typ.) 0 112lsb 32 128lsb 63 144lsb cbch black level shift in ycbcr mode the cbch black level voltage can be set by a 6-bit dac during ycbcr signal input. the cbch black level voltage can be varied within the range of 16lsb centering on the adc input dynamic range center ((vrt + vrb)/2). register: ycbcr mode input signal mode 1 ycbcr register: cr offset level shift amount (typ.) 0 112lsb 32 128lsb 63 144lsb crch black level shift in ycbcr mode the crch black level voltage can be set by a 6-bit dac during ycbcr signal input. the crch black level voltage can be varied within the range of 16lsb centering on the adc input dynamic range center ((vrt + vrb)/2).
44 CXA3516R input signal connection method input pin no. pin 124 pin 126 pin 133 pin 136 pin 139 pin 141 g/yin1 g/yin2 b/cbin1 b/cbin2 r/crin1 r/crin2 68 to 75 78, 81 to 85, 87, 88 45 to 49, 51 to 53 56 to 58, 60 to 64 21, 22, 24 to 28, 31 34 to 41 ga0 to ga7 gb0 to gb7 ba0 to ba7 bb0 to bb7 ra0 to ra7 rb0 to rb7 symbol output pin no. symbol 1. when inputting both rgb and ycbcr, input according to the table above. 2. syncsep is connected to g/yin. 3. when inputting rgb and not using syncsep, there is no difference between the three channels so the input order may be optional. 4. when inputting y, cb and cr, be sure to input according to the table above. it is possible for only the r/cr in and b/cb in pins to be clamped to the center of the adc input dynamic range.
45 CXA3516R syncsep the syncsep function can be used to separate and output the sync signal that is superimposed on the sync on green signal (including the sync on y signal). there are two major syncsep circuits. one is the circuit for creating a sync signal to be input to the pll, and the other is a circuit for outputting a sync signal from the sogout (pin 105) so that a clamp pulse can be created externally. these syncsep circuits perform processing on entirely different channels. (see the block diagram for the syncsep operational description.) syncsep circuit for the pll sync signal in the case of the sync on green signal, the sync on green signal is ac coupled to the g/yin1 (pin 124) or the g/yin2 (pin 126) and the sync component is separated and used as a reference. an input capacitor of 0.1f is recommended. when a signal is input to this pin, the pedestal level is clamped by a clamp pulse input to the clpin (pin 113). after this, the signal is split into a signal to the amplifier circuit and the signal to the syncsep circuits, and the sync signal is sent through a two lines of input select switch (sw sogp) and the sync signal is separated by the syncsep circuits. at this time, it is possible to minimize the jitter of the sync signal sent to the pll by using a control register to select the threshold level (v th ) and hysteresis level (v hys ) of the syncsep circuit according to the type of noise on the superimposed sync signal. sog sync sep threshold (versus pedestal level) the sync signal separated by the syncsep circuits can be switched at the sw pll circuit with an externally input sync signal (the sync signal input from the syncin1 or syncin2 pin) by using control registers (syncp/hsync). the selected signal is input to the pll block. selecting between the sync separated sync signal and the externally input sync signal sog sync sep hysteresis register: sync sep v th threshold 0000 75mv 9.3mv step 1111 215mv register: sync sep v hys hysteresis 00 2mv 01 20mv 10 45mv 11 70mv register: syncp/hsync in sync signal type sync signal input pin 01 sync separated signal g/yin1 pin g/yin2 pin externally input sync signal syncin1 pin syncin2 pin v th v hys pedestal level sync signal
46 CXA3516R syncsep circuits for the sync signal for the clamp pulse a sync on green signal is input to the sogin1 (pin 132) or sogin2 (pin 135). the ac coupled signal is internally sync tip clamped and the minimum level (bottom of sync) is turned into the internally-set dc level (approximately 2.8v). the sync tip clamped input signal is separated from the threshold of 165mv (at sync duty 5%) above from the bottom of the sync by the syncsep circuit. after this, the signal is output at ttl level from the sogout pin and used as a reference signal for generating a clamp pulse. since no clamp pulse is required for the sync tip clamp, it is possible to output a sync signal from the sogout pin even when there is no external clamp pulse present such as when power supply is turned on. an input capacitor of 0.1f is recommended. a control register can be used to select output either the sync signal separated out from the signal input from the sogin1 pin or the sogin2 pin by sw sog o or the previously described pll sync signal output from the sw pll circuit. output from the sogout pin synct1, synct2/syncp1, syncp2/syncin1, syncin2 output selection synct1, synct2: the sync signal sync tip clamped and separated from the sogin1 and sogin2 pins syncp1, syncp2: the sync signal pedestal clamped and separated from the g/yin1 and g/yin2 pins syncin1, syncin2: the sync signal input from the syncin1 and syncin2 pins register: sync out sw output from the sogout pin 0 synct1, synct2 1 syncp1, syncp2 or syncin1, syncin2 the sogin1, sogin2 and the previously described g/yin1, g/yin2 are interlocked as for the 2-ch selection (register: rgb in select). input channel selection register: rgb in select g/yin pin selection sogin pin selection 0 in1 in1 1 in2 in2 register: sogout pol sogout output polarity 0 negative 1 positive register: sog enable sogout output status 0 off 1 on the polarity of signals output from the sogout pin can be set by using registers. sync on green output enable when the sogout pin is not used, it is possible to turn off the ttl output using a control register. but it cannot be set to high impedance.
47 CXA3516R register: hsync1/2 sync signal input pin 0 syncin1 1 syncin2 register: sync pol sync signal input polarity 0 negative 1 positive pll sync signal input the sync (hsync) used by the pll is input from the sync signal input pins. there are two sets of input pins, syncin1 (pin 111) and syncin2 (pin 112), which are switched by the control register. syncin1 input, syncin2 input switching sync signals within the range from 10khz to 130khz can be input. the input supports both positive and negative polarity. sync signal input polarity set the register in accordance with the polarity of the externally input sync. when sync is positive polarity, set sync pol to "1". (clock is generated in sync with the rising edge of sync.) when sync is negative polarity, set sync pol to "0". (clock is generated in sync with the falling edge of sync.) when there is no sync input, the vco oscillates at random and a random pulse is output from the clk output. div 1, 2, 4 ,8 programmable counter vco cp lpf pd ab sync signal point a: vco oscillation frequency point b: clock frequency phase detector (pd) the phase detector compares the phase of the sync signal with that of the programmable counter output signal. the phase comparison is performed at the edge, and a phase difference between the compared signals is output as a pulse. there is no hysteresis function for the input pins of the sync signal (syncin1 and syncin2) input to the phase detector. if necessary external waveform shaping should be done as jitter results when a noisy signal is input. set the control register, pd pol, to "1" as for the input polarity of the phase detector. hold function the hold function holds the vco input voltage and generates oscillation itself without performing phase comparison. the vco oscillation frequency is held during this period without performing phase comparison, by inputting the hold signal from the hold (pin 106). hold signal polarity can be set by using the control register: hold pol. register: hold pol hold signal input polarity 0 held while hold signal is low held while hold signal is high 1 for details, see the hold timing diagram.
48 CXA3516R charge pump (cp) the charge pump sets charge pump current to flow for the amount of time corresponding to the pulse width output from the phase detector. the phase detector gain is determined by the charge pump current. the amount of current can be varied by using a control register. this ic is used to set the charge pump current value according to the vco oscillation frequency as given below. [cp setting matrix] vco oscillation frequency: cp setting values 40mhz to 85mhz: 200a 85mhz to 110mhz: 300a 110mhz to 140mhz: 400a 140mhz to 155mhz: 500a 155mhz to 165mhz: 600a the vco oscillation frequency is that at the point a in the diagram. register: charge pump bit2 register: charge pump bit1 register: charge pump bit0 charge pump current 0 0 0 100a 0 0 1 200a 0 1 0 300a 0 1 1 400a 1 0 0 500a 1 0 1 600a 1 1 0 700a 1 1 1 800a loop filter (lpf) the control voltage input to the vco is the pulse current output from the charge pump circuit that is smoothed by an integrating circuit (loop filter). the resistor and capacitor values of the integrating circuit are as follows. (for the circuit configuration, see the application circuit.) c1 = 0.33f c2 = 330pf r1 = 3.3k ? for the resistor and capacitors, use a metal film chip resistor with little temperature variation and ceramic chip capacitors. in particular, the 0.33f capacitor should be equivalent to high dielectric constant series capacitor type b or better. (electrostatic capacitance change ratio 10%: t = 25 to +85 c) in case of using any resistors or capacitors except those given above, it is not guaranteed. vco the vco oscillation frequency range covers from 40mhz to 165mhz.
49 CXA3516R register: clk enable, xclk enable clock output status 0 off 1 on vco frequency dividers (div 1, 2, 4, 8) the oscillation frequency of the vco can be divided to 1/1, 1/2, 1/4, or 1/8 according to a control register setting. depending on the combination of the vco oscillation frequency and vco frequency divider, the point b clock frequency covers an operating range of 5mhz to 165mhz. the matrix of the vco frequency divider setting is as follows. [vco frequency divider setting matrix] clock frequency: div setting value 5mhz to 14mhz: 1/8 14mhz to 40mhz: 1/4 40mhz to 80mhz: 1/2 80mhz to 120mhz: 1/1 register: div 1, 2, 4, 8 bit1 register: div 1, 2, 4, 8 bit0 counter frequency 0 0 1/1 0 1 1/2 1 0 1/4 1 1 1/8 programmable counter the clock frequency at point b is divided and a programmable counter output signal is generated. the frequency division ratio can be set optionally by using a 12-bit control register. this is determined by using lower order 3 bits and upper order 9 bits in the following formula. frequency division ratio = (m + 1) 8 + n m: 9 bits (vco div bit 3 to 11) n: 3 bits (vco div bit 0 to 2) register no. register 0 register 1 data7 msb m4 register name vcodiv1 vcodiv2 data6 m3 data5 m2 data4 m1 data3 m0 m8 data2 n2 m7 data1 n1 m6 data0 lsb n0 m5 after the set value for the frequency division ratio is changed, that set value is loaded into the programmable counter when the output value of the programmable counter becomes "all 0". clock output when the input polarity of the sync signal is positive, the clock output is synchronized to the rising edge of the sync signal and is available as complementary signals clk (pin 99) and xclk (pin 98). the delay time of the clock output can be varied in the range of 1/32clk to 64/32clk by using a control register (see pll timing diagram). although the clock output can be turned off independently by using a control register, it cannot be set to high impedance. the operational frequency of the clock is up to 100mhz.
50 CXA3516R register: dsync by-pass signal output from the dsync/divout pin 1 dsync signal 0 divout signal register: 1/2clk enable, 1/2xclk enable 1/2 clock output status 0 off 1 on 1/2 clock output 1/2 clock signal is a signal that resets the clock by using a reset pulse created from an internal delay sync signal and divides the clock in half. the complementary signal is output from the 1/2clk (pin 101) and 1/2xclk (pin 100). (see the pll timing diagram). although the 1/2 clock output can also be independently turned off by the control register, it cannot be set to high impedance. delay sync output two types of delay sync signal (dsync and divout) can be output from the dsync/divout (pin 103). this is selected by switching a control register. the dsync signal is output as the input sync signal undergone timing control. the divout signal is output as the programmable counter output undergone timing control. both can be used as reset signals for any connected ic such as a scaling ic. delay sync output signal (dsync/divout (pin 103)) dsync signal a sync signal input that has been timing controlled by a clock generated by a pll is output. although only the forward edge is completely managed at this time with delay settings, etc., the back edge has an undefined width for one clock cycle because it latches and outputs the input sync signal. divout signal a timing controlled programmable counter output signal is output. in addition to the coarse delay that has been set by using the dsync signal, the delay time setting is output with a delay of 4 or 5 clocks. the pulse width is also managed by a clock. [function correspondence table for the dsync signal/divout signal] function dsync signal divout signal register coarse delay fine delay pulse width divout delay output polarity output enable output during hold 3clk to 6clk 1/32clk to 64/32clk fixed (depends on input sync signal width) on/off on/off on/off 3clk to 6clk 1/32clk to 64/32clk 1, 2, 4, 8clk 4, 5clk on/off on/off on/off coarse delay fine delay divout width divout delay dsync pol dsync enable dsync hold
51 CXA3516R register: fine delay delay time 000000 1/32clk 000001 2/32clk 111111 64/32clk register: coarse delay delay time 00 3clk 01 4clk 10 5clk 11 6clk delay time setting (fine delay/coarse delay) the delay sync output, clock output, and 1/2 clock output can make delay time setting (fine delay/coarse delay) for the input signal. the amount of delay time is from 3clk delay to 6clk delay for coarse delay and from 1/32clk to 64/32clk for fine delay. the delay time (fine delay/coarse delay) can be set by using the control registers shown below. divout signal output pulse width the pulse width of the divout signal output can be set to 1, 2, 4, 8 clock pulse widths by using a control register. register: divout width dsync signal width 00 1clk 01 2clk 10 4clk 11 8clk register: divout delay delay time 0 4clk 1 5clk register: dsync pol delay sync output polarity 0 negative 1 positive divout signal output delay time setting the divout signal is output with 4 or 5 clock delay based on the delay time (fine delay/ coarse delay) set as described above. the clock delay time can be set by using a control register. delay sync output polarity the polarity of the delay sync signal output from the dsync/divout pin can be selected either negative or positive by using a control register. register: dsync enable delay sync output status 0 off 1 on delay sync output status although it is possible to turn off the signal output from the dsync/divout pin by using a control register, it cannot be set to high impedance.
52 CXA3516R register: dsync hold 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 h l h l h l h l l divout signal l dsync signal divout signal divout signal dsync signal dsync signal register: dsync by-pass hold signal logic (when hold pol register = 1) delay sync output delay sync output status during hold register: the delay sync output during the hold period can be controlled with the dsync hold register and the hold signal. register: dsync hold delay sync output status 0 using hold signal logic 1 dsync signal/divout signal xtload signal (reset signal) this input pin forces to reset the divider function of the programmable counter. since this signal is not normally used, leave it open or fix to high level. when it is used, this signal is in conjunction with the hold signal. see the note given later regarding the combined use of these signals. the values given in the above table are for when the dsync pol register is set to "1". the delay sync output status is reversed when dsync pol is set to "0". xtload pin programmable counter status l forcible reset h count the output status resulting from this setting differs based on status of the dsync by-pass register.
53 CXA3516R register: the dsync hold register and hold signal can be used to control the delay sync output during the hold period. the relationship between the delay sync output and the sync signal is shown below. (for each of case 1 to 3, the dsync pol register is "1". in addition, the dsync signal output and divout signal output can be switched by using the dsync by-pass register.) case 1 sync signal (sync pol = 1) hold signal (1) dsync hold = 1 (2) dsync hold = 0 dsync signal dsync signal divout signal divout signal
54 CXA3516R case 2 sync signal (sync pol = 1) hold signal (1) dsync hold = 1 (2) dsync hold = 0 dsync signal dsync signal divout signal divout signal
55 CXA3516R case 3 sync signal (sync pol = 1) hold signal (1) dsync hold = 1 (2) dsync hold = 0 dsync signal dsync signal divout signal divout signal
56 CXA3516R notes on using the hold signal and xtload signal (reset signal) if the cycle of the sync signal is lost, the phase difference between the sync signal and the programmable counter output in the phase detector will increase, and it will cause pll unlock. at this time, the hold signal is input to the hold (pin 106), phase comparison is stopped while the signal is high level (when the hold pol register is set to "1"), and the clock can be stably oscillated by holding the vco oscillation frequency. note, however, the correspondence differs depending on whether the number of locations where the sync signal period changes (the 0.5h region in the diagram) is odd or even. programmable counter vco div 1, 2, 4, 8 cp lpf pd sync signal clock output sync signal (sync pol = 0) h 0.5h 0.5h 0.5h 0.5h 1234 hh h hold signal programmable counter output signal 0.5h 0.5h 0.5h 8clk h 1 23 hh hh xtload signal (reset signal) programmable counter output signal ? "hsync" and "xtload" are synchronized tw (min) = 100ns sync signal (sync pol = 0) hold signal case 1: when the 0.5h region is even (correspondence with hold signal only) when the number of the 0.5h period is even, it is possible to hold the period of the programmable counter output stable by applying the hold signal before the frequency changes. this corresponds to the vertical blanking period of the composite sync (computer signal). case 2: when the 0.5h region is odd (correspondence with hold signal + xtload signal (reset signal)) when the number of the 0.5h period is odd, if only the hold signal is used, the phase difference between the sync signal and the programmable counter output signal will increase in the extra 0.5h region and the lock will be lost momentarily. in this case, the 0.5h region is held by the hold signal, and it is possible to use the xtload signal (reset signal) at 1h backward to the official counter period by resetting/setting the counter value. although there are no particular restrictions on the setup time and hold time of the xtload signal (reset signal), the pulse width of the xtload signal (reset signal) is restricted while the hold signal is high. (when the hold pol register is set to "1".) if the rising edge of the xtload signal (reset signal) is delayed by 8clk from the falling edge of the sync signal, counter output will be obtained by synchronizing with the falling edge of the next sync signal. see the diagram for details on timing.
57 CXA3516R hold signal timing sync signal (when sync pol = 1) sync signal (when sync pol = 0) hold signal (when hold pol = 1) divout signal (when dsync pol = 0) clock output thold ths thh ths thh vco oscillation frequency is held without performing phase comparison. the hold signal setup time (ths) is the time from the rising edge of the hold signal to the falling edge of the divout signal. the hold signal hold time (thh) is the time from the falling edge of the divout signal to the rising edge of the hold signal. see the above timing diagram for details on the relationship with sync pol. the frequency variation of clk while held can be calculated as given below. vco i leak c q +q ? v ? f i sw i sw c ? v = q = i leak thold c: loop filter capacitance ? v: varying voltage due to leak current i leak : leak current of the internal amplifier thold: hold time ? v = ileak thold/c ? f = ? v kvco = i leak thold/c kvco for example, assuming f = 100mhz, i leak = 1na, thold = 1ms, c = 0.33f, kvco = 2 55 [mhz/v], ? v = 1 10 9 1 10 3 /(0.1 10 6 ) = 3 10 6 [v] ? f = 1 10 9 1 10 3 /(0.1 10 6 ) 2 70 10 6 = 1050 [hz]
58 CXA3516R unlock detect unlock signal vcc vcc r2 r3 50k ? q1 r1 = 100 ? r2 = 100k ? c1 = 0.01 f ic external ic internal r1 i1 i2 s2 signal s1 signal c1 signal from the phase detector 104 the unlock output is an open collector. by connecting the external circuit shown above to this output pin, it is possible to adjust the sensitivity of the s2 signal by varying the constants r1, r2 and c1. (the constants r1, r2 and c1 above are reference values. the resistor r3 should be 50k ? and q1 should be 2sc series. the operations of the three cases are described below. case 1: when there is no phase difference (pll locked status) the s1 signal is low and the s2 signal is high. the unlock signal is low. unlock timing if the phase difference between the sync signal input and the programmable counter output signal to the phase detector (pd) increases, it becomes impossible for the vco to maintain stable oscillation. this status is converted into the unlock signal and output. it is possible to perform analog lock/unlock by connecting an external circuit to this pin. s1 signal s2 signal unlock signal h h l h l l threshold level of the inverter s1 signal s2 signal unlock signal h h l h l l threshold level of the inverter case 2: when there is a phase difference, the s1 signal will goes low and high as shown in the figure below. at this time, the falling edge slew rate of the s2 signal is determined by the current i1 flowing into this open collector. the falling edge slew rate of the s2 signal will therefore be delayed as resistor r1 increases. in addition, since the rising edge slew rate of the s2 signal is determined by the current i2, the rising edge slew rate of the s2 signal will become faster as the resistor r2 decreases. if the integrated s2 signal does not fall below the threshold level of the next inverter, the unlock signal will remain low. this will therefore be judged as locked even if there is a phase difference. s1 signal s2 signal unlock signal h h l h l l threshold level of the inverter case 3: however, even if the same phase difference as described above is assumed, the decreasing resistor r1 will increase the current i1 flowing into the open collector. the falling edge slew rate of the s2 signal will therefore become faster. in addition, if resistor r2 is increased, the rising edge slew rate of the s2 signal will become slower. if the integrated s2 signal is under the threshold level of the next inverter, the unlock signal will go from low to high and the pll will be judged as unlocked.
59 CXA3516R the CXA3516R's charge pump is a constant-current output type as shown below. s1 v cc to lpf s2 when a constant-current output charge pump circuit is used inside the pll, the phase detector (pd) output acts as a current source, and the dimension of its transmittance kpd is a/rad. also, when considering the vco input as a voltage, the lpf transmittance dimension must be expressed in ohms ( ? = v/a). therefore, the pll transmittance when a constant-current output charge pump circuit is used is as follows. 1/s kpd (a/rad) pd kvco (rad/s/v) vco lpf counter f (s) ( ? ) 1/s 1/n + o n 0 0 /n r r the pll closed loop transmittance is obtained by the following formula. here, kpd, f(s) and kvco are: kpd: phase comparator gain (a/rad) f(s): loop filter transmittance ( ? ) kvco: vco gain (rad/s/v) ? 1 the reason for the 1/s inside the phase detector is as follows. o (t)/n = 0 (t)/ndt + o (t = 0)/n: (a) o (t = 0) = 0 o (t)/n = 0 (t)/ndt: (b) performing laplace conversion: o (s)/n = w 0 (s)/n: (c) 1 s o/n r kpd f (s) kvco 1/n 1/s 1 + kpd f (s) kvco 1/n 1/s = ... (1) t o t o
60 CXA3516R the loop filter f(s) is described below. the loop filter smoothes the output pulse from the phase detector (pd) and inputs it as the dc component to the vco. in addition to this, however, the loop filter also functions as an important element in determining the pll response characteristics. typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. however, the CXA3516R's lpf is a current input type active filter as shown below, so the following calculations show an actual example of deriving the pll closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants. current input type active filter i i cr vo vo a 1 the filter transmittance is as follows. + vo = (r + ) i i f (s) = = = rc here, assuming a > 1, then: f (s) = ........................ (2) next, substituting (2) into (1) and obtaining the overall closed loop transmittance for the pll: = ... (3) = ................................................. (4) n = ................................................. (5) = n ..................................................................... (6) the bode diagram for formula (2) is as follows. 0 90 45deg log 1 log log scale gain [db] phase [deg] 2 ? ns + n 2 s 2 + 2 ? ns + n 2 1 + src sc a 1 + a 1 + s sc o/n r s + 1 + s sc a 1 + a kpd kvco nc kpd kvco nc s + s 2 + kpd kvco nc kpd kvco nc kpd kvco nc vo a 1 sc 1 2
61 CXA3516R here, n and are as follows. n characteristic angular frequency: the oscillatory angular frequency when pll oscillation is assumed to have been maintained by the loop filter and individual loop gains is called the characteristic angular frequency: n. damping factor: this is the pll transient response characteristic, and serves as a measure of the pll stability. it is determined by the loop gain and the loop filter. a capacitor c2 is added to the actual loop filter. this added capacitor c2 is used to reduce the r noise, and a value of around 1/10 to 1/1000 of c1 should be selected as necessary. current input type active filter with added capacitor c2 i i c1 r vo vo c2 a 1 the filter transmittance is as follows. f (s) = = ................... (3) 1 = c1 r 2 = here, assuming c2 = c1/100, then: 2 = = c1 r = 1 the bode diagram for formula (3) is as follows. 0 90 45deg log 1 1 1 2 log log scale gain [db] phase [deg] 1 + c1 r s s ((c1 + c2) + c1 c2 r s) 1 + 1 s s (c1 + c2) (1 + 2 s) c1 c2 r c1 + c2 c1 c1/100 r c1 + c1/100 1 101 1 101
62 CXA3516R next, the various parameters inside an actual CXA3516R are obtained. the CXA3516R's charge pump output block and the lpf circuit are as follows. v cc 100 a to to 800 a 100 a step s1 r1 c1 c2 s2 20k 100 333 CXA3516R to vco 100 a 800 a 100 a step 118 119 first, kpd is as follows. kpd = 100/2 or 200/2 or 300/2 or 400/2 or 500/2 or 600/2 or 700/2 or 800/2 (a/rad) typical kvco characteristics curves for the CXA3516R's internal vco are as follows. 200 150 100 50 2 3 vco div = 1/1 vco input voltage [v] vco frequency [mhz] 4 vco div = 1/2 vco div = 1/4 vco div = 1/8 therefore, kvco is as follows. kvco = 2 55 or 2 27.5 or 2 13.75 or 2 6.875 (rad/s/v)
63 CXA3516R khz mhz a bit2 bit1 bit0 m/(s ? v) bit1 bit0 f k ? khzrad khz mhz mode resolution fsync fclk kpd 2 c.pump setting kvco /2 div 1, 2, 4, 8 setting n setting c1 r1 n fn vco oscillation frequency ntsc ntsc ntsc ntsc pal pal pal pal 480p 1080i 720p pc-98 vga mac vesa svga svga svga svga svga mac xga xga xga mac xga sxga sxga sxga sxga uxga 640 400 640 480 640 480 640 480 800 600 800 600 800 600 800 600 800 600 832 624 1024 768 1024 768 1024 768 1024 768 1024 768 1280 1024 1280 1024 1280 1024 1280 1024 1600 1200 15.73 15.73 15.73 15.73 15.63 15.63 15.63 15.63 31.47 33.75 45.00 24.82 31.47 35.00 37.86 35.16 37.88 46.88 48.08 53.67 49.72 48.36 56.48 60.02 60.24 68.68 46.43 63.98 79.98 91.15 75.00 12.27 18.41 24.55 27.00 14.69 22.03 29.38 27.00 72.00 74.25 74.25 21.05 25.18 30.24 31.50 36.00 40.00 49.51 50.00 56.25 57.28 65.00 75.01 78.75 80.00 94.50 78.75 108.00 135.01 156.96 162.00 300 200 300 300 200 300 400 300 500 500 500 200 300 400 400 500 600 300 300 400 400 400 500 600 600 300 600 300 400 600 600 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 55/8 55/4 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/4 55/4 55/4 55/4 55/4 55/4 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/2 55/1 55/2 55/1 55/1 55/1 55/1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 780 1170 1560 1716 940 1410 1880 1728 2288 2200 1650 848 800 864 832 1024 1056 1056 1040 1048 1152 1344 1328 1312 1328 1376 1696 1688 1688 1722 2160 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 0.33 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 2.83 2.67 2.83 2.70 2.98 2.98 2.98 2.69 4.27 4.35 5.03 3.13 3.95 4.39 4.48 4.51 4.87 4.87 4.90 5.64 5.38 4.98 5.60 6.17 6.14 6.03 5.43 5.44 6.28 7.62 6.80 0.45 0.42 0.45 0.43 0.47 0.47 0.47 0.43 0.68 0.69 0.80 0.50 0.63 0.70 0.71 0.72 0.77 0.77 0.78 0.90 0.86 0.79 0.89 0.98 0.98 0.96 0.86 0.87 1.00 1.21 1.08 1.54 1.45 1.54 1.47 1.62 1.62 1.62 1.46 2.32 2.37 2.74 1.71 2.15 2.39 2.44 2.46 2.65 2.65 2.67 3.07 2.93 2.71 3.05 3.36 3.34 3.28 2.96 2.96 3.42 4.15 3.70 98.18 73.64 98.18 108.00 58.75 88.13 117.50 108.00 144.01 148.50 148.50 84.19 100.70 120.96 126.00 144.02 160.01 99.01 100.01 112.49 114.55 129.99 150.01 157.49 160.00 94.50 157.49 108.00 135.01 156.96 162.00 n and calculated for various types of computer signals are shown below. here, the various parameters are as follows. fsync: input sync frequency, fclk: output clock frequency kpd 2 : phase comparator gain 2 (kpd 2 = 100 or 200 or 300 or 400 or 500 or 600 or 700 or 800) kvco/2 : vco gain (when vco div = 1/1, kvco/2 = 55) (when vco div = 1/2, kvco/2 = 55/2) (when vco div = 1/4, kvco/2 = 55/4) (when vco div = 1/8, kvco/2 = 55/8) n: counter value, c1: loop filter capacitance value, r1: loop filter resistance value cp setting matrix internal vco oscillation frequency: cp setting value 40mhz to 85mhz: 200a 85mhz to 110mhz: 300a 110mhz to 140mhz: 400a 140mhz to 155mhz: 500a 155mhz to 165mhz: 600a div setting matrix output oscillation frequency: div setting value 5mhz to 14mhz: 1/8 14mhz to 40mhz: 1/4 40mhz to 80mhz: 1/2 80mhz to 165mhz: 1/1
64 CXA3516R clk jitter evaluation method the generated clk is obtained by inputting hsync to the CXA3516R. apply this clk to a digital oscilloscope and observe the clk waveform using hsync as the trigger. pulse generator CXA3516R clock hsync signal ch1 trigger digital oscilloscope trigger enlarge enlarge enlarge enlarge clock tj p-p active video front porch back porch h sync clock hsync signal tsync = 1/fsync 15 to 25% of tsync computer signal the clk jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure. the clk jitter size varies according to the difference in the relative position with respect to hsync. therefore, when the observation point is changed, the clk jitter at that point is observed. the figure below shows a typical example of the clk jitter for the CXA3516R. the clk jitter increases slightly at the rising edge of hsync (in the case of positive polarity), and then settles down thereafter. however, this is not a problem as the active pixels start after about 20% of the h cycle has passed from the rising edge of hsync. jitter amount tj p-p observation points 2/4 tsync 1/4 tsync 0 3/4 tsync tsync
65 CXA3516R a/d converter analog input signal the rgb analog input signal and ycbcr analog input signal are converted to digital signals and output. be sure to adjust the input dynamic range of the adc in the pre-stage amplifier block by performing contrast and brightness settings for the analog signal input to the adc. (see the item on the amplifier for details on the setting procedure.) sampling clock although the sampling clock is created by a pll (internal clk), it is also possible to externally input a clock to the adc (external clk) directly for checking adc operations. in this case, be sure to make the register settings below in order to input a pecl level clock from the clkin (pin 110) and the xclkin (pin 109). register: vco by-pass adc clock 0 external clk 1 internal clk note, however, that even if an external clk is input under the above settings, it is impossible to run the adc at the input clock frequency unless the pll's vco frequency divider is set to 1/1. running the adc on an external clk is done in order to check the operations of the adc. normally, it should be run on the internal clk generated by the pll. reference voltage the input dynamic range of the adc is determined based on the reference voltage from the vrt (pin 17) and the vrb (pin 93). since this reference voltage is created using an internal band gap voltage, there is no need for an external reference voltage circuit. the voltage at the vrt pin is set to a voltage approximately 0.4v lower than the voltage coming from the av cc ad3 power pin. also, the vrb pin is set to a voltage approximately 1.0v lower than that at the vrt pin. capacitors of 1f or more should be connected between the av cc ad3 power supply pins for these reference voltage pins (vrt pin and vrb pin). if the value of the capacitor is too low or no capacitor is attached, the reference voltage circuit will cause an oscillation that results in noise or malfunction because the adc faithfully samples this oscillation. it is impossible to apply an external voltage to a reference voltage pin. note that it is also impossible to use the voltage generated by a reference voltage pin as an external voltage source. operational mode the adc output data of this ic supports five types of operational mode. each operational mode is set by using a control register. straight data out mode dmux parallel data out mode dmux interleaved data out mode 4:2:2 data out d2 mode 4:2:2 data out special mode register: data out mode d3 d2 d1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 for a description of each operational mode, see the next page.
66 CXA3516R description of the operational modes (straight data out mode) an rgb analog input signal ac coupled is optimized by using a 3-ch amp and the signal is input to the adc. the analog input signal input to the adc is sampled by using a clock generated by the pll. the identical signal with the sampling clock for analog input signal is output from the clk (pin 99). the sampled analog input signal is output from the port a side of the data output with a 3-clock pipeline delay. note that output for port b side is turned off at this time and cannot be set to high impedance. the adc data output is output with a propagation delay (td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the clk pin. the operational frequency in straight data out mode is 100mhz at the sampling clock frequency. also, note, when operating in straight data out mode, that the output on the port b side (rb0 to rb7, gb0 to gb7, and bb0 to bb7) is turned off and cannot be set to high impedance. all ttl output are set to high impedance only when this ic is put into power save mode. the following type of interface is possible when this ic is operated in straight data out mode. the hold time of the post-stage scaling ic using the interface shown above is, th (min.) = 2.2ns CXA3516R scaling ic clk xclk 1/2clk 1/2xclk 99 98 101 100 ra0 to ra7 ga0 to ga7 ba0 to ba7 max. min. td_8 2.2ns (min.) to 3.8ns (max.) th (min.)
67 CXA3516R (dmux parallel data out mode) the rgb analog input signal ac coupled is optimized by using a 3-ch amp and the signal is input to the adc. the analog signal input to the adc is sampled by using a clock generated by the pll. the identical signal with the sampling clock for analog input signal is output from the clk (pin 99). at each clock cycle, sampled data is divided into pins in port a side and port b side. the data output on the port a side possesses a 3-clock pipeline delay versus the sampling clock, while the data output on the port b side possesses a 2-clock pipeline delay. the output timing is the same for data output from both ports. data is maintained for two cycles (2t) of the sampling clock. adc data is output with a propagation delay (td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2xclk (pin 100). an interface of the following type is possible when this ic is run in dmux parallel data out mode. CXA3516R scaling ic clk xclk 1/2clk 1/2xclk 99 98 101 100 ra0 to ra7 ga0 to ga7 ba0 to ba7 rb0 to rb7 gb0 to gb7 bb0 to bb7 ts max. min. th ts th t td_7 1.3ns (min.) to 2.2ns (max.) with the interface shown above, the post-stage scaling ic acquire data by using the clock signal output from the 1/2clk pin of the adc. in case of this interface, the setup time of the post-stage scaling ic is, ts (min.) = t 2.2ns while the hold time is, th (min.) = t + 1.3ns
68 CXA3516R (dmux interleaved data out mode) the rgb analog input signal ac coupled is optimized by using a 3-ch amp and the signal is input to the adc. the analog signal input to the adc is sampled by using a clock generated by the pll. the identical signal with the sampling clock for analog input signal is output from the clk (pin 99). at each clock cycle, sampled data is divided into pins in port a and port b. the data output on the port a side possesses a 2-clock pipeline delay versus the sampling clock, while the data output on the port b side also possesses a 2-clock pipeline delay. although the data output from both ports is maintained for two cycles (2t) of the sampling clock, there is one cycle (t) difference between the output timing for port a side and port b side. data output on port a side possesses a propagation delay (td_7) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2xclk (pin 100), while data output on port b side possesses a propagation delay (td_1/2clk to data) ranges from 1.3ns (min.) to 2.2ns (max.) versus the clock output from the 1/2clk (pin 101). an interface of the following type is possible when this ic is run in dmux interleaved data out mode. CXA3516R scaling ic clk xclk 1/2clk 1/2xclk 99 98 101 100 ra0 to ra7 ga0 to ga7 ba0 to ba7 rb0 to rb7 gb0 to gb7 bb0 to bb7 ts max. min. th ts th t max. min. ? td ? td ? td td_7 1.3ns (min.) to 2.2ns (max.) with the interface shown above, port a data is acquired into the post-stage scaling ic by using the clock signal output from the 1/2clk pin of the adc, while port b data is acquired by using the clock signal output from the 1/2xclk pin. in case of this interface, the setup time of the post-stage scaling ic is, ts (min.) = t 2.2ns while the hold time is, th (min.) = t + 1.3ns
69 CXA3516R (4:2:2 data out d2 mode) the ycbcr analog input signal ac coupled is optimized by using a 3-ch amp and the signal is input to the adc. the analog signal input to the adc is sampled by using a clock generated by the pll. the identical signal with the sampling clock for analog input signal is output from the clk (pin 99). in 4:2:2 data out d2 mode, the only y signal is a/d converted just as in straight data out mode and output to the data output ports ga0 to ga7. the cb and cr signals are all simultaneously a/d converted at a half sampling rate compared with the y signal, then multiplexed within the ic, and output to the data output ports ba0 to ba7 in the order u (cb) and v (cr). when the sync on y signal is input, it is necessary to separate out the sync signal superimposed on the signal. see the operational description of syncsep for details. data output of adc possesses a propagation delay (td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the clk pin. the operating frequency in 4:2:2 data out d2 mode is 100mhz as the sampling clock frequency. although ra0 to ra7, rb0 to rb7, gb0 to gb7, and bb0 to bb7 are all put into output off mode when the ic operates in 4:2:2 data out d2 mode, they cannot be set to high impedance. all ttl output is set to high impedance when this ic is put into power save mode. an interface of the following type is possible when this ic is run in 4:2:2 data out d2 mode. the hold time of the post-stage scaling ic using the interface shown above is, th (min.) = 2.2ns CXA3516R scaling ic clk xclk 1/2clk 1/2xclk 99 98 101 100 ga0 to ga7 ba0 to ba7 max. min. td_8 2.2ns (min.) to 3.8ns (max.)
70 CXA3516R (4:2:2 data out special mode) the ycbcr analog input signal ac coupled is optimized by using a 3-ch amp and the signal is input to the adc. the analog input signal to the adc is sampled by using a clock generated by the pll. the identical signal with the sampling clock for analog input signal is output from the clk (pin 99). in 4:2:2 data out special mode, the only y signal is a/d converted just as in straight data out mode and output to the data output ports ga0 to ga7. the cb and cr signals are a/d converted at every other sampling at a half sampling rate of the y signal, then multiplexed within the ic, and output to the data output ports ba0 to ba7 in the order u (cb) and v (cr). when the sync on y signal is input, it is necessary to separate out the sync signal superimposed on the signal. see the operational description of syncsep for details. adc data output possesses a propagation delay (td_8) ranges from 2.2ns (min.) to 3.8ns (max.) versus the clock output from the clk pin. the operating frequency in 4:2:2 data out special mode is 100mhz as the sampling clock frequency. in addition, although ra0 to ra7, rb0 to rb7, gb0 to gb7, and bb0 to bb7 are all put into output off mode when the ic operates in 4:2:2 data out special mode, they cannot be set to high impedance. all ttl output is set to high impedance when this ic is put into power save mode. an interface of the following type is possible when this ic is run in 4:2:2 data out d2 mode. the hold time of the post-stage scaling ic using the interface shown above is, th (min.) = 2.2ns CXA3516R scaling ic clk xclk 1/2clk 1/2xclk 99 98 101 100 ga0 to ga7 ba0 to ba7 max. min. td_8 2.2ns (min.) to 3.8ns (max.)
71 CXA3516R even/odd function when a toggle signal created by dividing the vsync signal in half is input to the even/odd (pin 108), the adc sampling clock is inverted every vsync signal. this function can be used to configure a single frame screen from two fields by ad converting an rgb analog input signal that requires high speed and high resolution, such as a uxga 60hz (162mhz) or more signal, at half the frequency of the original adc sampling rate. there are no particular control register settings when using the even/odd function. the sampling clock is inverted based on the polarity of the signal input to the even/odd pin. be sure to input signal to the even/odd pin at ttl level. even/odd pin operational mode l even h odd example of using the even/odd function 2 4 6 1 3 5 a b c d e f g h i j k l 1 3 even field odd field even/odd frame 5 a b c d e f g h i j k l 2 4 6 a b c d e f g h i j k l 1 3 5 2 4 6 analog input signal hsync sampling clk vsync toggle signal (even/odd pin)
72 CXA3516R ttl output high level setting all the ttl output pins can be set to high level by the control register. all the ttl output pins are set simultaneously. the ttl output pins are as follows. ra7 to ra0, rb7 to rb0, ga7 to ga0, gb7 to gb0, ba7 to ba0, bb7 to bb0, serout, sogout, delay sync output, 1/2clk, 1/2xclk, clk and xclk register: ttlout clp high level (typ.) 00 2.2v 01 2.45v 10 2.7v 11 2.95v the ttl output can be input directly to a 3v power supply ic without level conversion. set high level in accordance with the supply voltage. power save 1) power save for all functions all functions of the chip can be stopped to save power by the xpower save (pin 6). the control register is also set to power save mode at this time. xpower save pin operating status l power save h power on register adc power save amp power save pll power save sync sep power save 0 power on power on power on power on 1 power save power save power save power save the pin input level is ttl level. 2) power save every block by using the control register the blocks except the registers can also be set to power save mode by the control register. selects according to using state.
73 CXA3516R ttl output mode during power save mode all ttl output pins are set to high impedance when the ic is put into power save mode. since this ic supports power on reset, amp, adc, pll, and syncsep are set to power save mode when power is turned on and all ttl output pins are set to high impedance. however, note that the ttl output pins don't change into high impedance, when control register are used to set each ttl output disable mode separately. even though there are also modes in which data output ports are set to output off mode based on the adc operational mode, it cannot be set to high impedance. adc data output modes other ttl output pin modes ra7 to 0 rb7 to 0 ga7 to 0 gb7 to 0 ba7 to 0 bb7 to 0 xpower save mode hi-z hi-z hi-z hi-z hi-z hi-z adc power save mode straight mode dmux parallel mode dmux interleaved mode yuv 4:2:2 d2 mode yuv 4:2:2 special mode hi-z hi-z hi-z hi-z hi-z hi-z data ? data ? data ? data data data data data data data data data data data data ? ? data ? data ? ? ? data ? data ? clk xclk 1/2clk 1/2xclk dsync/ divout sogout serout unlock xpower save mode hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z pll power save mode clk disable xclk disable 1/2clk disable 1/2xclk disable sogout disable hi-z hi-z hi-z hi-z hi-z hi-z hi-z hi-z ? signal signal signal signal signal signal signal signal ? signal signal signal signal signal signal signal signal ? signal signal signal signal signal signal signal signal ? signal signal signal signal signal signal signal signal ? signal signal signal dsync disable signal signal signal signal signal ? signal signal signal signal signal signal signal signal ? signal serout disable signal signal signal signal signal signal signal ? unlock disable ? a dash ( ) indicates output off status that cannot be set to high impedance.
74 CXA3516R supply current the default value for the current consumption and the control register-based power save current (i cc5ps , i cc3ps ), and power save current (i cc5xps , i cc3xps ) when the xpower save function is used, are indicated to each block as follows. (the current consumption values given here are the typical values for when the ic is run at a clock frequency of 80msps.) block register amp (syncsep) pll adc dv cc reg av cc amp ? av cc vco + av cc ir dv cc pll + dv cc pllttl av cc adref dv cc ad + dv cc adttl av cc ad3 + dv cc ad3 5v (d) 5v (a) 5v (a) 5v (d) 5v (a) 5v (d) 3.3v (a) 17.2ma 80.0ma 16.0ma 41.4ma 6.8ma 73.2ma 180ma 17.2ma 0.7ma 0ma 2.0ma 0.4ma 6.0ma 3.0ma 1.2ma 0.7ma 0ma 1.0ma 0.4ma 6.0ma 3.0ma supply pin names supply voltage current consumption (typ.) register ps current consumption xps current consumption av cc amp ? = av cc ampr + av cc ampg + av cc ampb
75 CXA3516R pll timing chart (td1 = 3clk) analog input syncin1 (pin 111) syncin2 (pin 112) dsync signal (pin 103) (dsync by-pass = 1) divout signal (pin 103) (dsync by-pass = 0, divout delay = 0) divout signal (pin 103) (dsync by-pass = 0, divout delay = 1) 1/2clk (pin 101) (n = odd) adc data output (straight mode) 1/2clk (pin 101) (n = even) reset (internal signal) n 2 0 1 2 3 4 5 6clk n 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n 5 n 4 n 3 n 2 n 1 n n + 1 n + 2 n + 3 td_2 = 1/32 to 64/32clk td_1 = 3clk td_5 = 5clk 1, 2, 4, 8clk 1, 2, 4, 8clk td_5 = 4clk td_4 (typ. 1.0ns) td_3 (typ. 7ns) td_6 (typ. 1.2ns) td_6 (typ. 1.2ns) clk (pin 99) 1clk
76 CXA3516R pll timing chart (td1 = 4clk) analog input syncin1 (pin 111) syncin2 (pin 112) dsync signal (pin 103) (dsync by-pass = 1) divout signal (pin 103) (dsync by-pass = 0, divout delay = 0) divout signal (pin 103) (dsync by-pass = 0, divout delay = 1) 1/2clk (pin 101) (n = odd) adc data output (straight mode) 1/2clk (pin 101) (n = even) reset (internal signal) clk (pin 99) n 2 0 1 2 3 4 5 6clk n 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n 5 n 4 n 3 n 2 n 1 n n + 1 n + 2 n + 3 td_2 = 1/32 to 64/32clk td_1 = 4clk td_5 = 5clk 1, 2, 4, 8clk 1, 2, 4, 8clk td_5 = 4clk td_4 (typ. 1.0ns) td_3 (typ. 7ns) td_6 (typ. 1.2ns) td_6 (typ. 1.2ns) 1clk
77 CXA3516R pll timing chart (td1 = 5clk) analog input syncin1 (pin 111) syncin2 (pin 112) dsync signal (pin 103) (dsync by-pass = 1) divout signal (pin 103) (dsync by-pass = 0, divout delay = 0) divout signal (pin 103) (dsync by-pass = 0, divout delay = 1) 1/2clk (pin 101) (n = odd) adc data output (straight mode) 1/2clk (pin 101) (n = even) reset (internal signal) clk (pin 99) n 2 0 1 2 3 4 5 6clk n 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n 5 n 4 n 3 n 2 n 1 n n + 1 n + 2 n + 3 td_2 = 1/32 to 64/32clk td_1 = 5clk td_5 = 5clk 1, 2, 4, 8clk 1, 2, 4, 8clk td_5 = 4clk td_4 (typ. 1.0ns) td_3 (typ. 7ns) td_6 (typ. 1.2ns) td_6 (typ. 1.2ns) 1clk
78 CXA3516R pll timing chart (td1 = 6clk) analog input syncin1 (pin 111) syncin2 (pin 112) dsync signal (pin 103) (dsync by-pass = 1) divout signal (pin 103) (dsync by-pass = 0, divout delay = 0) divout signal (pin 103) (dsync by-pass = 0, divout delay = 1) 1/2clk (pin 101) (n = odd) adc data output (straight mode) 1/2clk (pin 101) (n = even) reset (internal signal) clk (pin 99) n 2 0 1 2 3 4 5 6clk n 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n 5 n 4 n 3 n 2 n 1 n n + 1 n + 2 n + 3 td_2 = 1/32 to 64/32clk td_1 = 6clk td_5 = 5clk 1, 2, 4, 8clk 1, 2, 4, 8clk td_5 = 4clk td_4 (typ. 1.0ns) td_3 (typ. 7ns) td_6 (typ. 1.2ns) td_6 (typ. 1.2ns) 1clk
79 CXA3516R adc timing diagram 0.9ns to 1.2ns to 1.6ns td_6 min. typ. max. 2.2ns to 2.8ns to 3.8ns td_8 min. typ. max. min. typ. max. t r_clk 0.8ns 1.4ns 2.3ns t f_clk 1.0ns 1.5ns 2.8ns min. typ. max. t r_clk 0.8ns 1.4ns 2.3ns t f_clk 1.0ns 1.5ns 2.8ns min. typ. max. t r_data 0.9ns 1.2ns 2.0ns t f_data 0.9ns 1.2ns 2.0ns 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v clock clk xclk 1/2clk 1/2xclk 1/2 clock data the timing diagram above supposes that one data cycle represents the same amount of time as one clock cycle concerning the three modes as follows: straight data out mode, 4:2:2 data out d2 mode, and 4:2:2 data out special mode.
80 CXA3516R adc timing diagram 0.9ns to 1.2ns to 1.6ns td_6 min. typ. max. 2.3ns to 2.6ns to 3.2ns td_7 min. typ. max. min. typ. max. t r_clk 0.8ns 1.4ns 2.3ns t f_clk 1.0ns 1.5ns 2.8ns min. typ. max. t r_clk 0.8ns 1.4ns 2.3ns t f_clk 1.0ns 1.5ns 2.8ns min. typ. max. t r_data 0.9ns 1.2ns 2.0ns t f_data 0.9ns 1.2ns 2.0ns 2.0v 0.8v 2.0v 0.8v 2.0v 0.8v clock clk xclk 1/2clk 1/2xclk 1/2 clock data t t 2.2ns min. t + 1.3ns min. the timing diagram above supposes dmux parallel data out mode. it is possible for the post-stage scaling ic to acquire data by using a 1/2 clock. the output delay time in this mode is the same as that in dmux interleaved data out mode.
81 CXA3516R adc timing diagram (straight data out mode) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n1 n0 n2 n3 n4 n5 n6 n7 n8 n9 n10 n7 n6 n5 n4 n3 n2
82 CXA3516R adc timing diagram (dmux parallel data out mode) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n1 n0 n2 n3 n4 n5 n6 n7 n8 n9 n10 n6 n4 n2 n7 n5 n3
83 CXA3516R adc timing diagram (dmux interleaved data out mode) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n1 n0 n2 n3 n4 n5 n6 n7 n8 n9 n10 n7 n5 n3 n6 n4 n2
84 CXA3516R adc timing diagram (4:2:2 data out d2 mode) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) data out ga7 to ga0 ba7 to ba0 syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) y1 y0 y2 y3 y4 y5 y6 y7 y8 y9 y10 cb1 cb3 cb5 cb7 cb9 cr1 cr3 cr5 cr7 cr9 y8 y6 y4 y2 y3 y5 y7 cb3 (u3) cr3 (v3) cb5 (u5) cr5 (v5) cb7 (u7) cr7 (v7)
85 CXA3516R adc timing diagram (4:2:2 data out special mode) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) data out ga7 to ga0 ba7 to ba0 syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) y1 y0 y2 cr2 y3 y4 y5 y6 y7 y8 cr4 cr6 cr8 y9 y10 cr10 cb1 cb3 cb5 cb7 cb9 y8 y6 y4 y2 y3 y5 y7 cb3 (u3) cr2 (v3) cr4 (v4) cb5 (u5) cr6 (v6) cb7 (u7) cr8 (v8)
86 CXA3516R adc timing diagram (straight data out mode, even/odd) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n0 n4 n5 n3 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n2 n1 n14 n10 n6 n4 n8 n12 data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n0 n4 n5 n3 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n2 n1 n11 n7 n5 n9 n13 data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 even odd
87 CXA3516R adc timing diagram (dmux parallel data out mode, even/odd) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n0 n4 n5 n3 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n2 n1 n8 n4 n12 n10 n6 n14 data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n0 n4 n5 n3 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n2 n1 n5 n9 n13 n7 n11 n15 data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 even odd
88 CXA3516R adc timing diagram (dmux interleaved data out mode, even/odd) analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n0 n4 n5 n3 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n2 n1 n10 n6 n14 n8 n4 n12 data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 analog input rin1 (139 pin) rin2 (141 pin) gin1 (124 pin) gin2 (126 pin) bin1 (133 pin) bin2 (136 pin) syncin1 (111 pin) syncin2 (112 pin) dsync (103 pin) clk (99 pin) xclk (98 pin) 1/2clk (101 pin) 1/2xclk (100 pin) n0 n4 n5 n3 n6 n7 n8 n9 n10 n11 n12 n13 n14 n15 n16 n17 n18 n19 n20 n21 n2 n1 n7 n11 n15 n5 n9 n13 data out ra7 to ra0 ga7 to ga0 ba7 to ba0 rb7 to rb0 gb7 to gb0 bb7 to bb0 even odd
89 CXA3516R 0 0 0.5 1.0 1.5 gain [db] 2.0 2.5 50 100 150 main contrast register main contrast control characteristics 200 250 sub contrast = 128 r, g, b out 0 30 20 10 0 gain adjustment ratio [%] 10 20 30 50 100 150 sub contrast register sub contrast control characteristics 200 250 main contrast = 128 r, g, b out 0 80 60 40 20 0 20 ad output conversion level (lsb) 40 60 80 50 100 150 brightness register brightness level control characteristics 200 250 0 100 105 110 115 125 120 ad output conversion level (lsb) 135 130 145 140 150 10 20 30 40 cbcr offset register cbcr clamp level control characteristics 50 60 0 0 50 100 150 v th [mv] 200 250 2 46 810 v th register sync sep v th control characteristics 12 14 0 0 10 20 40 30 v hys [mv] 50 70 60 80 12 v hys register sync sep v hys control characteristics 3
90 CXA3516R 0.1 5 3 1 1 3 5 gain [db] 7 9 110 frequency [mhz] frequency response 100 300 main contrast = 128 sub contrast = 128 r, g, b out 10 10 8 6 4 2 0 2 gain fluctuation ratio [%] 4 6 8 10 0 10 20 30 40 50 ta ambient temperature [ c] gain temperature characteristics 60 70 10 0 10 20 30 40 50 60 70 4.75 2.0 1.5 1.0 0.5 0 0.5 gain fluctuation ratio [%] 1.0 1.5 2.0 5 supply voltage [v] gain supply voltage characteristics 5.25 4.75 5 5.25 0.3 0.2 0.1 0.1 0 ad output fluctuation (lsb) 0.3 0.2 0.5 0.4 0.6 0.6 0.4 0 0.2 0.2 0.4 0.6 ta ambient temperature [ c] brightness level temperature characteristics 1.5 1.0 0.5 0 0.5 ad output level fluctuation (lsb) 1.0 1.5 supply voltage [v] brightness supply voltage characteristics ad output level fluctuation (lsb) cbcr clamp level temperature characteristics main contrast = 128 sub contrast = 128 r, g, b out brightness = 128 10 0 10 20 30 40 50 60 70 ta ambient temperature [ c] main contrast = 128 sub contrast = 128 r, g, b out brightness = 128 cbcr offset register = 32
91 CXA3516R 1.5 0 50 100 150 output frequency [mhz] 200 250 2.0 2.5 3.0 3.5 4.0 4.5 vco control voltage [v] kvco characteristics 5.0 0 0 8 16 24 32 40 48 fine delay [1/32clk] 56 72 64 80 32 40 48 56 8 16 24 fine delay register control [1/32clk] fine delay vs. control 64 div = 1/1 div = 1/2 div = 1/4 div = 1/8 0.6 0.4 0 0.2 0.2 0.4 0.6 ad output level fluctuation (lsb) cbcr clamp level supply voltage characteristics 4.75 5 5.25 supply voltage [v] cbcr offset register = 32 ntsc, div = 1/8, cp = 010, 100 vga, div = 1/4, cp = 010, 011 svga, div = 1/4, 1/2, cp = 010, 100, 101 xga, div = 1/2, cp = 011, 100 sxga, div = 1/1, cp = 010, 011, 100 uxga, div = 1/1, cp = 101 020 40 60 80 100 120 140 160 180 0 0.4 0.2 0.6 1.0 0.8 jitter peak-peak [ns] 1.4 1.2 1.8 1.6 2.0 output frequency [mhz] jitter peak-peak vs. output frequency
92 CXA3516R 3.0 160 180 current consumption [ma] 200 3.3 5.0 5.25 4.75 supply voltage [v] ta ambient temperature [ c] current consumption vs. supply voltage fluctuation 3.6 v cc 3 v cc 5 10 160 180 current consumption [ma] 200 0 25 50 current consumption vs. temperature characteristics 75 i cc 5 i cc 3 clk = dc i cc 5 i cc 3 clk = dc 160 180 200 220 240 260 current consumption [ma] fclk clock frequency [mhz] current consumption vs. frequency response 100 120 160 20 140 40 60 80 i cc 5 i cc 3 operational mode: dmux parallel data out load capacitance: c l = 10pf
93 CXA3516R application circuit (i 2 c (high) mode) 0.1 75 0.1 75 0.1 75 0.1 75 0.1 0.1 0.1 0.1 75 0.1 g1 g2 b1 r1 r2 b2 1 1 100p 100p c1 0.33 r1 3.3k 3k c2 330p 75 0.1 0.1 4.7k 4.7k av cc 5v dv cc 5v 3.3v dgnd agnd 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 1 2 3 4 121 122 123 124 125 126 127 128 129 130 131 132 142 143 144 110 109 111 112 113 114 115 116 117 118 119 120 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 36 11 21 31 b/cbout address r/crout nc nc xpower save dgndreg dv cc reg sda scl xsenable serout 3wire/i 2 c dpgnd av cc adref av cc ad3 vrt dv cc ad3 dv cc adttl dgndadttl ra0 ra1 dgndad3 ra2 ra3 ra4 ra5 ra6 agndad3 dgndad3 ra7 dv cc adttl dgndadttl rb0 rb1 rb2 ga4 ga3 ga2 ga1 ga0 dgndadttl dgndad3 dv cc adttl bb7 bb6 bb5 bb4 bb3 gndad3 bb2 bb1 bb0 dgndadttl dv cc adttl ba7 ba6 ba5 dgndad3 ba4 ba3 ba2 ba1 ba0 dgndadttl dgndad3 dv cc adttl rb7 rb6 rb5 rb4 rb3 even/odd xtload hold sogout unlock dsync/divout dpgnd 1/2clk 1/2xclk clk xclk dgndpllttl dv cc pllttl agndadref av cc ad3 vrb dv cc ad3 dv cc ad dv cc adttl dgndadttl gb7 gb6 dgndad3 gb5 gb4 gb3 gb2 gb1 agndad3 dgndad3 gb0 dgndadttl dv cc adttl ga7 ga6 ga5 xclkin clkin syncin1 syncin2 clpin dv cc pll dgndpll av cc vco agndvco rc1 rc2 av cc ir iref dpgnd agndir g/yin1 av cc ampg g/yin2 agndampg g/yclp b/cbclp r/crclp dpgnd sogin1 b/cbin1 av cc ampb sogin2 b/cbin2 agndampb dpgnd r/crin1 av cc ampr r/crin2 agndampr g/yout dactestout this is an application circuit which controls this ic with i 2 c (high) mode and supports rgb2 channel input. adc operational mode supports dmux parallel mode or dmux interleaved mode. (i 2 c bus slave address is 10011000.) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
94 CXA3516R application circuit (3-wire bus mode) this is an application circuit which controls this ic with 3-wire bus mode and operates adc with 4:2:2 data out d2 mode with respect to ycbcr analog input signal. 820 0.1 75 0.1 75 0.1 0.1 0.1 0.1 y cb cr 1 1 100p 100p c1 0.33 r1 3.3k 3k c2 330p 75 0.1 4.7k 820 tp-r tp-b tp-g 820 4.7k av cc 5v dv cc 5v 3.3v dgnd agnd 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 133 134 135 136 137 138 139 140 141 1 2 3 4 121 122 123 124 125 126 127 128 129 130 131 132 142 143 144 110 109 111 112 113 114 115 116 117 118 119 120 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 32 33 34 35 36 11 21 31 b/cbout address r/crout nc nc xpower save dgndreg dv cc reg sda scl xsenable serout 3wire/i 2 c dpgnd av cc adref av cc ad3 vrt dv cc ad3 dv cc adttl dgndadttl ra0 ra1 dgndad3 ra2 ra3 ra4 ra5 ra6 agndad3 dgndad3 ra7 dv cc adttl dgndadttl rb0 rb1 rb2 ga4 ga3 ga2 ga1 ga0 dgndadttl dgndad3 dv cc adttl bb7 bb6 bb5 bb4 bb3 gndad3 bb2 bb1 bb0 dgndadttl dv cc adttl ba7 ba6 ba5 dgndad3 ba4 ba3 ba2 ba1 ba0 dgndadttl dgndad3 dv cc adttl rb7 rb6 rb5 rb4 rb3 even/odd xtload hold sogout unlock dsync/divout dpgnd 1/2clk 1/2xclk clk xclk dgndpllttl dv cc pllttl agndadref av cc ad3 vrb dv cc ad3 dv cc ad dv cc adttl dgndadttl gb7 gb6 dgndad3 gb5 gb4 gb3 gb2 gb1 agndad3 dgndad3 gb0 dgndadttl dv cc adttl ga7 ga6 ga5 xclkin clkin syncin1 syncin2 clpin dv cc pll dgndpll av cc vco agndvco rc1 rc2 av cc ir iref dpgnd agndir g/yin1 av cc ampg g/yin2 agndampg g/yclp b/cbclp r/crclp dpgnd sogin1 b/cbin1 av cc ampb sogin2 b/cbin2 agndampb dpgnd r/crin1 av cc ampr r/crin2 agndampr g/yout dactestout application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
95 CXA3516R notes on operation on the pc board, prepare a solid ground pattern having as large an area as possible, and placing the ic in the center, divide this area into an analog region and digital region. the loop filter area of the pll block plays an important role in terms of performance. it is therefore located as close as possible to the ic pins and the periphery is guarded with agnd. also, be sure to use capacitors and resistors for the loop filter that should be temperature compensated and do not change the values. be sure to use a metal film resistor for the resistor connected to iref (pin 121). the wiring for syncin1 (pin 111) and syncin2 (pin 112) should be as short as possible and each needs to be shielded by ground. use a 0.1f ceramic chip capacitor for the bypass capacitor attached between the power supply and ground. the capacitor should be attached to the pin as close as possible. use a 1f ceramic chip capacitor for the capacitor attached to the vrt (pin 17) and the vrb (pin 93) and connect to the av cc ad3 (pin 16 and pin 94) as close as possible. equalize and shorten the lines of rgb analog input signals, if possible. each line needs to be shielded by ground. (this is the same for the r/crclp, g/yclp, and b/cbclp pins.) a 0.1f capacitor is recommended for attachment to the rgb analog input pins. the less the capacitance becomes, the more the sag by leak current becomes. the more the capacitance becomes, the more start up time takes in case of putting power souce into the ic. (this is the same for the r/crclp, g/yclp, and b/cbclp pins.) design boards so that the wiring for the r/crin, g/yin, and b/cbin and r/crout, g/yout, b/cbout pins is as separated as possible. use a pattern width that takes characteristic impedance into account for signal wires terminated at 75 ? . there are no particular restrictions on the power-on sequence. although there are av cc ad3 and dv cc ad3 as 3.3v power supply, use the same 3.3v analog power supply to each on the board. agndad3 and dgndad3 are the ground for av cc ad3 and dv cc ad3, respectively. use the same ground for agndad3 and dgndad3. although agnd is the ground recommended for agndad3 and dgndad3, there are no problems in terms of operation even if connected to dgnd. (the special evaluation board in the application circuit is connected to dgnd.) although 5v power supply is divided into both analog and digital power supply lines, be sure to wire boards so that no potential difference arises between these power supplies. load capacitance of the data output wires causes the change for the worse of slew rate and noise. be sure to use short layouts with the finest wires possible. put this ic into power save mode when making a connection between data output and another ic. (high impedance cannot be set when pins are disabled separately.)
96 CXA3516R CXA3516R evaluation board overview the CXA3516R evaluation board is a special board designed for the easy evaluation of the CXA3516R developed for the lcd projector and monitor so that performance can be maximized. the dsub 15-pin connector is used as the input connector that allows the direct input of a video signal from a pc. the input video signal is a/d converted by the CXA3516R and a pin for monitoring is designed onto the board so that output data can be checked directly. the 10-bit high speed d/a converters are built onto the board so that the performance of the ic can be easily checked. picture quality can be easily evaluated by using a crt monitor since the d/a-converted video signal is output from the dsub 15-pin connector for output in addition to the dsync output of the CXA3516R. features single +5v power supply (with built-in 3.3v regulator) allows two-line video signal input data output port is also used as output data monitoring pin CXA3516R output is d/a converted and is easily monitored by a crt supports 2 types of control registers (3-wire and i 2 c) operating conditions supply voltage: +5v (typ.) current consumption: 830ma (typ.) input signal: separated sync video signal
97 CXA3516R CXA3516R evb block diagram 10 f 0.1 f 0.1 f vsync signal select video signal output hsync output vsync output video signal 2 hsync signal 2 vsync signal 2 video signal 1 hsync signal 1 vsync signal 1 r, g, b analog input signal r, g, b analog input signal r, g, b analog output signal r, g, b digital output data control signal 3 cxa3197r control register pins con5 3wire i 2 c con4 power supply pins output data monitoring pins data output ports video in1 con1 video in2 video signal input pins con2 video out con3 video signal output pins sogout clpin sw1 power save sw2 3wire/i 2 c sw3 i/o logic CXA3516R cxa2016p clamp pulse generation 5v 0v dac
98 CXA3516R using the CXA3516R evaluation board the CXA3516R evaluation board can be used to easily evaluate just by connecting a power supply, video signals, and control register signals. the procedure is described below. 1. connect the power supply to the power connection pin. (gnd/+5v) do not apply power supply in this state. 2. check the direction of sw1. sw1 is the power save control switch. the CXA3516R is put into power save mode when sw1 is set to the rear position ( ). set sw1 to the forward ( ) position when using the CXA3516R. sw1 is connected to the xpower save pin. 3. connect the special control register signal cable. connect the cable to con4 when using i 2 c control. set sw2 and sw3 to the forward ( ) position. while, connect the cable to con5 when using 3-wire control. set sw2 and sw3 to the rear ( ) position. in addition, check that the short pin (i 2 c) is in the "00" position in case of using i 2 c control. 4. input the rgb analog signals from the con1 pin (video in 1). xga60 is recommended as the initial signal because the control program default value is set for the xga60. xga60: vsync 60hz hsync: video signal for 48khz n = 1344 5. the rgb analog signal for simple picture quality evaluations is output from the con3 pin (video out). be sure to connect the con3 pin to a crt monitor that can process a signal of xga60 or more. 6. turn on the power. check a current to be about 360ma flows through the 5v power supply. if there is much more current than this, immediately turn off the power and check that there are no misconnections. 7. run the control program. click on "re-load" at the bottom right of the control program screen, and check a current to be about 830ma flows through the 5v power supply. if everything works normally, an processed image for picture quality evaluation appears on the crt monitor. reconfirm the above items from the beginning if the processed image does not appear.
99 CXA3516R 3-wire control program installation and startup method [operating environment] windows95 or windows98 [program installation and startup] the installation program is configured from the following four files and stored in two floppy disks. setup.exe, a3506_1.cab, a3506_2.cab, and setup.lst 1. copy the four files from the floppy disk onto the pc. 2. click setup.exe. the installer will start. follow all on-screen instructions. 3. once installation complete, a folder titled "project1" will be created in the program files folder. 4. the following control window will open when the a3506.exe file starts. use this window to make board settings in response to the printer port address of the pc. be sure to set the address for the pc from the pull-down menu port at the top-left of the control screen. there are two types of addresses: 378 and 3bc.
100 CXA3516R i 2 c control program installation and startup method [operating environment] windows95 or windows98 [program installation and startup] the installation program consists of the following four files and is stored in two floppy disks. setup.exe, a3506_1.cab, a3506_2.cab, setup.lst 1. copy these four files from the floppy disk onto the pc. 2. click setup.exe. the installer will start. follow all on-screen instructions. 3. once installation complete, a folder titled "project1" will be created in the program files folder. 4. the following control window will open when the a3506.exe file starts. use this window to make board settings in response to the printer port address of the pc. be sure to set the address for the pc from the pull-down menu port at the top-left of the control screen. there are two types of addresses: 378 and 3bc.
101 CXA3516R notes on using CXA3516R evb 1. rgb analog signals input from con1 or con2 are a/d converted. the digital signals are d/a converted. in addition, the analog signals are output in ac coupling. therefore, the output are the rgb analog signals output from con3. in this reason, when the rgb analog signals output from con3 undergo picture quality evaluation by using a crt monitor, note that on-screen evaluation cannot be confirmed about the functions of sub brightness and cb/cr offset. this is due to the fact that the dc component disappears because the rgb analog signals are output in ac coupled after output by the d/a converter, even if the dc offset is changed. 2. the current consumption for this board immediately after turning on the board's power is approximately 360ma. board current is 830ma when the CXA3516R control register is started after this. when turning on power to the board, be sure to check the board current and make sure that connections are correct. 3. although this board is equipped with a 5v power supply pin, it can operate by using a single 0/+5v power supply. be sure to leave the 5v power supply pin open. notes regarding the control program 1. when the program is accurately installed on the pc, be sure to re-check items 2 and 3 of the operational procedures above when the ic does not move. 2. if the CXA3516R does not move even after item 1 above is checked, it is possible that the control signals of the control register are not output from the pc printer board. in this case, be sure to re-check the board settings listed for item 4 under "program installation and startup".
102 CXA3516R CXA3516R evaluation board parts list parts no. product name manufacturer ic1 ic2 ic3, 4, 5 ic6 ic7 ic8 ic9 con1, 2, 3 con4 con5 sw1 sw2 sw3 l1, 2 CXA3516R cxa2016s cxa3197r sn74ls04n sn74ls32n sn74ls08n lt1086cm-3.3 d02-n15sag-13l9 53053-0510 53053-0610 g-12ap g-13ap g-22ap zbf503d-00 sony sony sony texas instruments texas instruments texas instruments linear technology sanshin electronics molex molex nihon kaiheiki ind. nihon kaiheiki ind. nihon kaiheiki ind. tdk r1, 2 r3, 4 r5 r6 r7 to 12 r13 to 15 r17, 18 r19 r20, 21 r22 r23 r24, 25, 27 r26, 29, 32 r28, 31, 34 r30, 33 r35 to 37 r38, 39 r40 to 44 r45 r47, 48 r49, 50 620 200 3.3k 3k 75 820 75 270 12k 33k 2.2k 1k 75 620 1k 24k 24k 10k 820 2k 3k chip resistor chip resistor chip metal film resistor lead metal film resistor chip resistor chip resistor chip resistor chip resistor lead metal film resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor chip resistor c1 to 4 c5 c6, 7 c8 to 10 c11, 12 c13, 14 c15 c16 c17 c18 to 34 c35 c36 to 44 c45 c47 c48, 49 c50 c51 c52 c53 c54 c55 to 70 c71 to 75 10 2.2 1 100 0.1 100p 0.1 330p 0.33 0.1 1 0.1 1 0.1 0.22 0.1 0.22 0.1 0.01 3300p 0.1 0.1 tantalum capacitor tantalum capacitor tantalum capacitor electrolytic capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor chip capacitor
103 CXA3516R b/cbout address r/crout nc nc xpower save dgndreg dvccreg sda scl xsenable serout 3wire/i 2 c dpgnd avccadref avccad3 vrt dvccad3 dvccadttl dgndadttl ra0 ra1 dgndad3 ra2 ra3 ra4 ra5 ra6 agndad3 dgndad3 ra7 dvccadttl dgndadttl rb0 rb1 rb2 ga4 ga3 ga2 ga1 ga0 dgndadttl dgndad3 dvccadttl bb7 bb6 bb5 bb4 bb3 gndad3 bb2 bb1 bb0 dgndadttl dvccadttl ba7 ba6 ba5 dgndad3 ba4 ba3 ba2 ba1 ba0 dgndadttl dgndad3 dvccadttl rb7 rb6 rb5 rb4 rb3 even/odd xtload hold sogout unlock dsync/divout dpgnd 1/2clk 1/2xclk clk xclk dgndpllttl dvccpllttl agndadref avccad3 vrb dvccad3 dvccad dvccadttl dgndadttl gb7 gb6 dgndad3 gb5 gb4 gb3 gb2 gb1 agndad3 dgndad3 gb0 dgndadttl dvccadttl ga7 ga6 ga5 xclkin clkin syncin1 syncin2 clpin dvccpll dgndpll avccvco agndvco rc1 rc2 avccir iref dpgnd agndir g/yin1 avccampg g/yin2 agndampg g/yclp b/cbclp r/crclp dpgnd sogin1 b/cbin1 avvampb sogin2 b/cbin2 agndampb dpgnd r/crin1 avccampr r/crin2 agndampr g/yout dac test out 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 ra4 ra3 ra2 ra1 ra0 gb7 gb6 gb5 gb4 gb3 gb2 gb1 gb0 ga7 ga6 ga5 ga4 ga3 ga2 ga1 ga0 bb7 bb6 bb5 bb4 bb3 c40 0.1 c39 0.1 c41 0.1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 c11 0.1 c12 0.1 c13 100p c14 100p c16 330p c17 0.33 r5 3.3k c20 0.1 c19 0.1 c21 0.1 c22 0.1 c23 0.1 c24 0.1 c25 0.1 c26 0.1 c27 0.1 c28 0.1 c30 0.1 c31 0.1 r7 75 r8 75 r9 75 r11 75 r10 75 r12 75 r6 3k c15 0.1 c18 0.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 bb0 bb1 bb2 c37 0.1 c34 0.1 c35 1 c36 0.1 c38 0.1 c33 0.1 r15 820 r14 820 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 sogout dsync 1/2clk 1/2xclk clk xclk rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 ra7 ra6 ra5 c43 0.1 c47 0.1 c44 0.1 c45 1 c42 0.1 agnd dgnd 3v even/odd xtload unlock dvcc dgnd avcc 3v agnd sda dgnd dvcc scl senable serout rout bout gout r13 820 s2 s3 s4 s1 slave address 10010 00 10010 10 10010 11 10010 01 r36 24k r37 24k r35 24k dvcc dgnd sw1 xpower save sw2 3-wire/i 2 c r39 24k r38 24k dvcc dgnd con1 video in1 agnd 11 con2 video in2 agnd agnd 15 5 6 1 dvcc avcc agnd agnd avcc agnd avcc agnd avcc agnd agnd avcc dgnd avcc agnd c32 0.1 c29 0.1 r1 620 r3 200 r2 620 avcc vsync2 vsync1 clamp agnd r4 200 video signal register rgb data 10 11 15 5 6 1 10 ic1 CXA3516R
104 CXA3516R clk/t clkp/e clkn/e clk/t clkp/e clkn/e clk/t clkp/e clkn/e db3 db2 db1 db0 div2in div2out clk/t clkp/e clkn/e reset/t resetp/e resetn/e 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 da6 da7 da8 da9 dgnd1 nc dvcc1 ps inv rpolarity voclp agnd2 db4 db5 db6 db7 db8 db9 da0 da1 da2 da3 da4 da5 12 11 10 9 8 7 6 5 4 3 2 1 rb2 rb3 rb4 rb5 rb6 rb7 ra0 ra1 ra2 ra3 ra4 ra5 ra6 ra7 rb0 rb1 25 26 27 28 29 30 31 32 33 34 35 36 dgnd2 c1 c2 c3 dvcc2 avcco aoutn aoutp agnd2 vref vset avcc2 ic3 cxa3197r dgnd agnd 1/2clk r27 1k c58 0.1 r28 620 c68 0.1 r26 75 c57 0.1 c56 0.1 dgnd dvcc c59 0.1 db3 db2 db1 db0 div2in div2out clk/t clkp/e clkn/e reset/t resetp/e resetn/e 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 da6 da7 da8 da9 dgnd1 nc dvcc1 ps inv rpolarity voclp agnd2 db4 db5 db6 db7 db8 db9 da0 da1 da2 da3 da4 da5 12 11 10 9 8 7 6 5 4 3 2 1 gb2 gb3 gb4 gb5 gb6 gb7 ga0 ga1 ga2 ga3 ga4 ga5 ga6 ga7 gb0 gb1 25 26 27 28 29 30 31 32 33 34 35 36 dgnd2 c1 c2 c3 dvcc2 avcco aoutn aoutp agnd2 vref vset avcc2 ic4 cxa3197r dgnd 1/2clk r30 1k c62 0.1 r31 620 c69 0.1 r29 75 c61 0.1 c60 0.1 dgnd dvcc c63 0.1 db3 db2 db1 db0 div2in div2out clk/t clkp/e clkn/e reset/t resetp/e resetn/e 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 da6 da7 da8 da9 dgnd1 nc dvcc1 ps inv rpolarity voclp agnd2 db4 db5 db6 db7 db8 db9 da0 da1 da2 da3 da4 da5 12 11 10 9 8 7 6 5 4 3 2 1 bb2 bb3 bb4 bb5 bb6 bb7 ba0 ba1 ba2 ba3 ba4 ba5 ba6 ba7 bb0 bb1 25 26 27 28 29 30 31 32 33 34 35 36 dgnd2 c1 c2 c3 dvcc2 avcco aoutn aoutp agnd2 vref vset avcc2 ic5 cxa3197r dgnd 1/2clk r33 1k c66 0.1 r34 620 c70 0.1 r32 75 c65 0.1 c64 0.1 dgnd dvcc c67 0.1 vsin pvc evc csin phc ehc videoin hdsel isc isj agnd ic2 cxa2016s avcc vd vssin vssout hd pv ph clpsel xclpout clpout vssref 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 c48 0.22 c49 0.22 c50 0.1 c51 0.22 r19 270 r23 2.2k r17 75 r18 75 r48 2k r50 3k r47 2k c74 0.1 c75 0.1 r49 3k c5 2.2 c6 1 c7 1 r20 12k r21 12k r22 33k agnd avcc agnd agnd dgnd dvcc clkp/e clkn/e clk sogout xclk c53 0.01 c52 0.1 c54 3300p c55 0.1 r24 1k r25 1k clamp s8 s7 avcc agnd av ee s10 s9 rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 gb7 gb6 gb5 gb4 gb3 gb2 gb1 gb0 ga7 ga6 ga5 ga4 ga3 ga2 ga1 ga0 bb7 bb6 bb5 bb4 bb3 bb2 bb1 bb0 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 rb7 rb6 rb5 rb4 rb3 dsync 1/2clk 1/2xclk clk xclk dsync 1/2clk 1/2xclk clk xclk rb2 rb1 rb0 ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 gb7 gb6 gb5 gb4 gb3 gb2 gb1 gb0 ga7 ga6 ga5 ga4 ga3 ga2 ga1 ga0 bb7 bb6 bb5 bb4 bb3 bb2 bb1 bb0 ba7 ba6 ba5 ba4 ba3 ba2 ba1 ba0 11 con3 video out 15 5 6 1 c8 100 c9 100 c10 100 video in1 vsync vsync1 vsync2 s5 s6 dsync video in2 vsync video signal rgb data 10
105 CXA3516R 3v v1 +5v agnd v2 0v dgnd senable scl sda serout dvcc dgnd dgnd av ee v3 5v register dvcc avcc c1 10 c2 10 c4 10 c3 10 gnd vout vin 1 2 3 l1 l2 ic9 lt1086cm-3.3 1 6 con4 i 2 c 1 5 con5 3-wire sda scl senable serout 74as04 ic6a 74as04 74as04 ic6b ic6e 74as04 ic6f 74as04 ic6c 9 8 5 6 6 2 1 5 ic8a 74as08 ic8b 74as08 ic7a 74as32 4 3 3 2 310 11 13 12 1 4 1 2 74as04 ic6d r40 10k sda scl r41 10k c71 0.1 c72 0.1 c73 0.1 r42 10k r43 10k r44 10k r45 820 sw6 3-wire/i 2 c dvcc dgnd
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110 CXA3516R sony corporation package outline unit: mm sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin 42/copper alloy lqfp-144p-l01 lqfp144-p-2020 1.3 g 144pin lqfp (plastic) 0.1 0.05 (21.0) 0.5 0.15 0 to 10 detail a 1 36 37 72 73 108 109 144 b 0.5 m 0.08 1.7 max 1.4 0.1 a b 0.1 s s 22.0 0.2 20.0 0.1 s detail b : palladium 0.125 0.04 b = 0.20 0.03 (0.125) 0.145 0.04 b = 0.22 0.05 (0.2) detail b : solder solder / palladium plating note : palladium plating this product uses s-pdppf (sony spec.-palladium pre-plated lead frame).

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